Simulation Results: csrng

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.23 %
  • code
  • 92.27 %
  • assert
  • 94.54 %
  • func
  • 65.89 %
  • block
  • 96.95 %
  • line
  • 97.62 %
  • branch
  • 92.43 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 22.000s 44.746us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 4.000s 355.895us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 13.665us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 25.000s 1688.723us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 46.742us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 36.014us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 13.665us 1 1 100.00
csrng_csr_aliasing 3.000s 46.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
alerts 1 1 100.00
csrng_alert 22.000s 2226.985us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 80.063us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 80.063us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 29.000s 1661.637us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 14.560us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 241.838us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 17.000s 159.991us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 17.000s 159.991us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 4.000s 355.895us 1 1 100.00
csrng_csr_rw 2.000s 13.665us 1 1 100.00
csrng_csr_aliasing 3.000s 46.742us 1 1 100.00
csrng_same_csr_outstanding 28.000s 29.778us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 4.000s 355.895us 1 1 100.00
csrng_csr_rw 2.000s 13.665us 1 1 100.00
csrng_csr_aliasing 3.000s 46.742us 1 1 100.00
csrng_same_csr_outstanding 28.000s 29.778us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 39.000s 605.601us 1 1 100.00
csrng_tl_intg_err 10.000s 159.978us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 28.000s 1.219us 0 1 0.00
csrng_csr_rw 2.000s 13.665us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 22.000s 2226.985us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 29.000s 1661.637us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
csrng_sec_cm 39.000s 605.601us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
csrng_sec_cm 39.000s 605.601us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
csrng_sec_cm 39.000s 605.601us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
csrng_sec_cm 39.000s 605.601us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
csrng_sec_cm 39.000s 605.601us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 22.000s 2226.985us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 29.000s 1661.637us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 22.000s 2226.985us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 10.000s 159.978us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
csrng_sec_cm 39.000s 605.601us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
csrng_sec_cm 39.000s 605.601us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 6.000s 261.949us 1 1 100.00
csrng_err 2.000s 31.118us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10802.093s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 93879147657031668072862217565430327776534118496051554501739562130745299143450 100
UVM_INFO @ 80063069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 81933772041500441369499890035985358183248629993026613868815750179064431118734 99
UVM_INFO @ 1219125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 82814862474655427011581377468690970131336983744687302395041500788166574650077 None