Simulation Results: edn/edn1

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.49 %
  • code
  • 84.41 %
  • assert
  • 98.70 %
  • func
  • 82.35 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 89.92 %
  • toggle
  • 94.99 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 17.328us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.960s 16.168us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 25.528us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.800s 196.847us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.280s 40.327us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.230s 24.077us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 25.528us 1 1 100.00
edn_csr_aliasing 1.280s 40.327us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.040s 140.094us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.040s 140.094us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.040s 140.094us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.840s 45.321us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 197.192us 1 1 100.00
errs 1 1 100.00
edn_err 1.060s 77.183us 1 1 100.00
disable 2 2 100.00
edn_disable 0.910s 39.133us 1 1 100.00
edn_disable_auto_req_mode 1.070s 62.979us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.530s 580.296us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 23.947us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.470s 49.187us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.260s 87.881us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.260s 87.881us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.960s 16.168us 1 1 100.00
edn_csr_rw 0.790s 25.528us 1 1 100.00
edn_csr_aliasing 1.280s 40.327us 1 1 100.00
edn_same_csr_outstanding 0.980s 61.074us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.960s 16.168us 1 1 100.00
edn_csr_rw 0.790s 25.528us 1 1 100.00
edn_csr_aliasing 1.280s 40.327us 1 1 100.00
edn_same_csr_outstanding 0.980s 61.074us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.180s 579.100us 1 1 100.00
edn_tl_intg_err 1.980s 457.025us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 28.858us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 197.192us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.180s 579.100us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.180s 579.100us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.180s 579.100us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.180s 579.100us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 197.192us 1 1 100.00
edn_sec_cm 2.180s 579.100us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 197.192us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.980s 457.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 63.990s 9166.804us 1 1 100.00