Simulation Results: flash_ctrl

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 94.14 %
  • assert
  • 96.93 %
  • func
  • 95.76 %
  • line
  • 96.00 %
  • branch
  • 97.19 %
  • cond
  • 93.79 %
  • toggle
  • 97.99 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
98.28%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 58.560s 132.926us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 14.170s 48.216us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 12.220s 122.606us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 12.960s 159.894us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 37.970s 6452.545us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 17.420s 876.970us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 18.640s 47.386us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 12.960s 159.894us 1 1 100.00
flash_ctrl_csr_aliasing 17.420s 876.970us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 8.140s 26.577us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.620s 17.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 17.390s 108.153us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 54.720s 249.864us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1217.150s 104770.090us 1 1 100.00
flash_ctrl_hw_rma_reset 625.790s 50130.931us 1 1 100.00
flash_ctrl_lcmgr_intg 6.290s 81.760us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1250.080s 640925.756us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 228.610s 2132.554us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.220s 37.783us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1669.600s 129002.099us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 41.420s 682.388us 1 1 100.00
rd_buff_eviction_w_ecc 2 3 66.67
flash_ctrl_rw_evict 15.840s 41.770us 1 1 100.00
flash_ctrl_rw_evict_all_en 15.450s 11.636us 0 1 0.00
flash_ctrl_re_evict 17.810s 603.761us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 86.690s 242.392us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 86.690s 242.392us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 263.790s 27045.670us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 13.300s 207.969us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 654.430s 945.530us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 522.130s 9950.630us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 308.370s 2256.088us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 927.950s 725.116us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.450s 42.438us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 181.650s 7566.982us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 13.410s 19.591us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 9.240s 50.570us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 106.190s 1088.540us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 127.300s 2096.764us 1 1 100.00
flash_ctrl_otp_reset 65.250s 141.842us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1217.150s 104770.090us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 92.310s 2732.055us 1 1 100.00
flash_ctrl_intr_wr 53.500s 6594.422us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 106.510s 36711.954us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 158.050s 25077.664us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 42.920s 4354.094us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 38.170s 4283.133us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 12.010s 26.502us 1 1 100.00
flash_ctrl_ro_derr 108.790s 2664.960us 1 1 100.00
flash_ctrl_rw_derr 158.760s 6139.528us 1 1 100.00
flash_ctrl_derr_detect 107.850s 1271.775us 1 1 100.00
flash_ctrl_integrity 402.830s 7178.159us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 16.720s 25.022us 1 1 100.00
flash_ctrl_ro_serr 97.550s 861.912us 1 1 100.00
flash_ctrl_rw_serr 169.800s 1844.583us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 68.300s 3138.307us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 40.940s 1045.439us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 147.300s 5010.691us 1 1 100.00
flash_ctrl_write_word_sweep 7.480s 96.116us 1 1 100.00
flash_ctrl_read_word_sweep 7.640s 48.667us 1 1 100.00
flash_ctrl_ro 85.500s 2653.414us 1 1 100.00
flash_ctrl_rw 368.750s 14976.760us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 25.570s 678.699us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 649.220s 131888.077us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 47.900s 10032.807us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.330s 66.493us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 8.650s 127.205us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 11.660s 115.933us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 11.660s 115.933us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.220s 122.606us 1 1 100.00
flash_ctrl_csr_rw 12.960s 159.894us 1 1 100.00
flash_ctrl_csr_aliasing 17.420s 876.970us 1 1 100.00
flash_ctrl_same_csr_outstanding 14.040s 375.117us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 12.220s 122.606us 1 1 100.00
flash_ctrl_csr_rw 12.960s 159.894us 1 1 100.00
flash_ctrl_csr_aliasing 17.420s 876.970us 1 1 100.00
flash_ctrl_same_csr_outstanding 14.040s 375.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 37.210s 124.874us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 37.210s 124.874us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 37.210s 124.874us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 37.210s 124.874us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 45.580s 152.781us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1758.440s 6613.606us 1 1 100.00
flash_ctrl_tl_intg_err 215.100s 849.808us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 215.100s 849.808us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 215.100s 849.808us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.160s 387.234us 1 1 100.00
flash_ctrl_wr_intg 7.840s 47.254us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 58.560s 132.926us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 65.250s 141.842us 1 1 100.00
flash_ctrl_disable 13.410s 19.591us 1 1 100.00
flash_ctrl_sec_info_access 40.200s 888.232us 1 1 100.00
flash_ctrl_connect 9.240s 50.570us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 8.430s 40.932us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 12.960s 159.894us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 37.210s 124.874us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 12.960s 159.894us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 37.210s 124.874us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 12.960s 159.894us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 37.210s 124.874us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 13.410s 19.591us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.160s 387.234us 1 1 100.00
flash_ctrl_access_after_disable 6.640s 40.064us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.170s 37.870us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 13.410s 19.591us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 13.300s 207.969us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 368.750s 14976.760us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 169.800s 1844.583us 1 1 100.00
flash_ctrl_rw_derr 158.760s 6139.528us 1 1 100.00
flash_ctrl_integrity 402.830s 7178.159us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1217.150s 104770.090us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.440s 6613.606us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.440s 6613.606us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.440s 6613.606us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1758.440s 6613.606us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.530s 686.704us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 6.030s 5.350us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 14.120s 304.263us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1758.440s 6613.606us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.440s 6613.606us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.440s 6613.606us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 19.870s 48.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 98.290s 762.670us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 1 test run
flash_ctrl_rw_evict_all_en 22723728059387364562432142660025170163535751501774219163686935834269701029809 108
UVM_INFO @ 11635.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 1 test run
flash_ctrl_phy_host_grant_err 25448936906516599620482121901859661532456894309347630686132683889884278589004 125
UVM_ERROR @ 5350.4 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 5350.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---