Simulation Results: hmac

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.39 %
  • code
  • 98.61 %
  • assert
  • 98.02 %
  • func
  • 44.55 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.170s 2907.319us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.690s 92.311us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.920s 12.358us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.360s 4307.879us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.990s 579.305us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.030s 83.118us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.920s 12.358us 1 1 100.00
hmac_csr_aliasing 6.990s 579.305us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 26.940s 3474.285us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 44.470s 11067.523us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.940s 2289.203us 1 1 100.00
hmac_test_sha384_vectors 411.510s 146021.923us 1 1 100.00
hmac_test_sha512_vectors 22.070s 513.931us 1 1 100.00
hmac_test_hmac256_vectors 7.850s 237.521us 1 1 100.00
hmac_test_hmac384_vectors 7.940s 1063.897us 1 1 100.00
hmac_test_hmac512_vectors 9.990s 484.884us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 22.140s 2369.163us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 197.930s 2756.078us 1 1 100.00
error 1 1 100.00
hmac_error 0.800s 271.635us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 26.440s 2906.993us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.170s 2907.319us 1 1 100.00
hmac_long_msg 26.940s 3474.285us 1 1 100.00
hmac_back_pressure 44.470s 11067.523us 1 1 100.00
hmac_datapath_stress 197.930s 2756.078us 1 1 100.00
hmac_burst_wr 22.140s 2369.163us 1 1 100.00
hmac_stress_all 871.550s 7252.595us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.170s 2907.319us 1 1 100.00
hmac_long_msg 26.940s 3474.285us 1 1 100.00
hmac_back_pressure 44.470s 11067.523us 1 1 100.00
hmac_datapath_stress 197.930s 2756.078us 1 1 100.00
hmac_wipe_secret 26.440s 2906.993us 1 1 100.00
hmac_test_sha256_vectors 8.940s 2289.203us 1 1 100.00
hmac_test_sha384_vectors 411.510s 146021.923us 1 1 100.00
hmac_test_sha512_vectors 22.070s 513.931us 1 1 100.00
hmac_test_hmac256_vectors 7.850s 237.521us 1 1 100.00
hmac_test_hmac384_vectors 7.940s 1063.897us 1 1 100.00
hmac_test_hmac512_vectors 9.990s 484.884us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.170s 2907.319us 1 1 100.00
hmac_long_msg 26.940s 3474.285us 1 1 100.00
hmac_back_pressure 44.470s 11067.523us 1 1 100.00
hmac_datapath_stress 197.930s 2756.078us 1 1 100.00
hmac_burst_wr 22.140s 2369.163us 1 1 100.00
hmac_error 0.800s 271.635us 1 1 100.00
hmac_wipe_secret 26.440s 2906.993us 1 1 100.00
hmac_test_sha256_vectors 8.940s 2289.203us 1 1 100.00
hmac_test_sha384_vectors 411.510s 146021.923us 1 1 100.00
hmac_test_sha512_vectors 22.070s 513.931us 1 1 100.00
hmac_test_hmac256_vectors 7.850s 237.521us 1 1 100.00
hmac_test_hmac384_vectors 7.940s 1063.897us 1 1 100.00
hmac_test_hmac512_vectors 9.990s 484.884us 1 1 100.00
hmac_stress_all 871.550s 7252.595us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 871.550s 7252.595us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.780s 110.831us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 20.201us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.770s 113.105us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.770s 113.105us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.690s 92.311us 1 1 100.00
hmac_csr_rw 0.920s 12.358us 1 1 100.00
hmac_csr_aliasing 6.990s 579.305us 1 1 100.00
hmac_same_csr_outstanding 1.230s 49.875us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.690s 92.311us 1 1 100.00
hmac_csr_rw 0.920s 12.358us 1 1 100.00
hmac_csr_aliasing 6.990s 579.305us 1 1 100.00
hmac_same_csr_outstanding 1.230s 49.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.010s 67.205us 1 1 100.00
hmac_tl_intg_err 2.250s 383.182us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.250s 383.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.170s 2907.319us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 0.940s 52.951us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 109.870s 6240.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.910s 252.059us 1 1 100.00