Simulation Results: keymgr

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.47 %
  • code
  • 94.33 %
  • assert
  • 97.49 %
  • func
  • 67.58 %
  • line
  • 98.68 %
  • branch
  • 97.44 %
  • cond
  • 94.36 %
  • toggle
  • 97.43 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.650s 502.172us 1 1 100.00
random 1 1 100.00
keymgr_random 2.730s 419.294us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.800s 52.458us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.080s 13.718us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 6.670s 2662.209us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.880s 431.585us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.960s 21.185us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.080s 13.718us 1 1 100.00
keymgr_csr_aliasing 3.880s 431.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 7.370s 389.489us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 3.780s 173.126us 1 1 100.00
keymgr_sideload_kmac 2.980s 405.300us 1 1 100.00
keymgr_sideload_aes 5.670s 284.011us 1 1 100.00
keymgr_sideload_otbn 2.840s 381.228us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 4.700s 2035.659us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.380s 96.987us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 4.360s 258.608us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.050s 57.195us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.500s 111.939us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.810s 305.144us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 30.710s 3335.333us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 1.000s 8.041us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.760s 31.697us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.780s 436.124us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.780s 436.124us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.800s 52.458us 1 1 100.00
keymgr_csr_rw 1.080s 13.718us 1 1 100.00
keymgr_csr_aliasing 3.880s 431.585us 1 1 100.00
keymgr_same_csr_outstanding 4.180s 114.545us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.800s 52.458us 1 1 100.00
keymgr_csr_rw 1.080s 13.718us 1 1 100.00
keymgr_csr_aliasing 3.880s 431.585us 1 1 100.00
keymgr_same_csr_outstanding 4.180s 114.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
keymgr_tl_intg_err 2.200s 188.285us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.850s 345.329us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.850s 345.329us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.850s 345.329us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.850s 345.329us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 6.770s 265.965us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 2.200s 188.285us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.850s 345.329us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 7.370s 389.489us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.730s 419.294us 1 1 100.00
keymgr_csr_rw 1.080s 13.718us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.730s 419.294us 1 1 100.00
keymgr_csr_rw 1.080s 13.718us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.730s 419.294us 1 1 100.00
keymgr_csr_rw 1.080s 13.718us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.380s 96.987us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.500s 111.939us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.500s 111.939us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.730s 419.294us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.290s 44.867us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.290s 114.489us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.380s 96.987us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.290s 114.489us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.290s 114.489us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.290s 114.489us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.500s 286.185us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.290s 114.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 3.280s 222.525us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 38216635702744061367618544235082905127769756909851667198533283503757605828388 428
UVM_INFO @ 222524773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---