Simulation Results: kmac/unmasked

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.43 %
  • code
  • 87.73 %
  • assert
  • 98.50 %
  • func
  • 91.05 %
  • line
  • 97.24 %
  • branch
  • 94.98 %
  • cond
  • 93.65 %
  • toggle
  • 99.87 %
  • FSM
  • 52.89 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 21.000s 1351.427us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.260s 41.810us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.300s 19.340us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 11.080s 615.845us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.530s 919.604us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.240s 371.630us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.300s 19.340us 1 1 100.00
kmac_csr_aliasing 5.530s 919.604us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.140s 12.633us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.650s 62.107us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2492.340s 199583.077us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 119.670s 7790.351us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1985.030s 418947.275us 1 1 100.00
kmac_test_vectors_sha3_256 23.820s 568.404us 1 1 100.00
kmac_test_vectors_sha3_384 21.560s 3203.425us 1 1 100.00
kmac_test_vectors_sha3_512 596.110s 18760.722us 1 1 100.00
kmac_test_vectors_shake_128 174.600s 16302.777us 1 1 100.00
kmac_test_vectors_shake_256 98.000s 13781.374us 1 1 100.00
kmac_test_vectors_kmac 2.060s 28.395us 1 1 100.00
kmac_test_vectors_kmac_xof 2.220s 221.614us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 315.920s 42706.729us 1 1 100.00
app 1 1 100.00
kmac_app 123.320s 6910.991us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 98.870s 23190.412us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 45.620s 19638.248us 1 1 100.00
error 1 1 100.00
kmac_error 154.230s 15566.277us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 4.160s 3669.006us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 74.280s 10013.450us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 13.460s 849.811us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 14.550s 8697.454us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 24.280s 5118.351us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 4.920s 533.844us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 754.340s 102034.279us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 1.100s 30.031us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.050s 50.276us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 4.880s 713.374us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 4.880s 713.374us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.260s 41.810us 1 1 100.00
kmac_csr_rw 1.300s 19.340us 1 1 100.00
kmac_csr_aliasing 5.530s 919.604us 1 1 100.00
kmac_same_csr_outstanding 2.450s 38.843us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.260s 41.810us 1 1 100.00
kmac_csr_rw 1.300s 19.340us 1 1 100.00
kmac_csr_aliasing 5.530s 919.604us 1 1 100.00
kmac_same_csr_outstanding 2.450s 38.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.350s 62.785us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.350s 62.785us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.350s 62.785us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.350s 62.785us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 1.870s 43.963us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 52.440s 5389.835us 1 1 100.00
kmac_tl_intg_err 3.340s 237.808us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.340s 237.808us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 4.920s 533.844us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 21.000s 1351.427us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 315.920s 42706.729us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.350s 62.785us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 52.440s 5389.835us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 52.440s 5389.835us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 52.440s 5389.835us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 21.000s 1351.427us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 4.920s 533.844us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 52.440s 5389.835us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 38.960s 6533.907us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 21.000s 1351.427us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 113.880s 14003.308us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 1 test run
kmac_sideload_invalid 19167632210561825017196634326943943339743368600694674769543052905309554129045 78
UVM_INFO @ 10013450482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---