Simulation Results: lc_ctrl/volatile_unlock_disabled

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.81 %
  • code
  • 82.95 %
  • assert
  • 94.13 %
  • func
  • 92.35 %
  • line
  • 97.15 %
  • branch
  • 93.56 %
  • cond
  • 79.17 %
  • toggle
  • 85.04 %
  • FSM
  • 59.81 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.110s 48.338us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.960s 45.680us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.940s 33.468us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.100s 71.939us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 75.609us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.970s 89.524us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.940s 33.468us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 75.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.900s 288.466us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.780s 831.101us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.330s 39.453us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.810s 88.045us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.770s 971.846us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.700s 298.333us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.770s 971.846us 1 1 100.00
lc_ctrl_prog_failure 1.810s 88.045us 1 1 100.00
lc_ctrl_errors 6.700s 298.333us 1 1 100.00
lc_ctrl_security_escalation 6.610s 1475.240us 1 1 100.00
lc_ctrl_jtag_state_failure 22.130s 4419.083us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.400s 325.935us 1 1 100.00
lc_ctrl_jtag_errors 57.070s 15597.887us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.460s 366.786us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.570s 338.564us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.400s 325.935us 1 1 100.00
lc_ctrl_jtag_errors 57.070s 15597.887us 1 1 100.00
lc_ctrl_jtag_access 8.250s 1721.937us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.330s 941.843us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.720s 311.988us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.240s 38.210us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 20.820s 940.716us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.720s 837.145us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.180s 69.650us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.570s 109.205us 1 1 100.00
lc_ctrl_jtag_alert_test 1.120s 25.485us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 15.830s 946.236us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.310s 13.898us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 203.790s 38965.992us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.070s 64.774us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.830s 109.151us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.830s 109.151us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 45.680us 1 1 100.00
lc_ctrl_csr_rw 0.940s 33.468us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 75.609us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 59.761us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 45.680us 1 1 100.00
lc_ctrl_csr_rw 0.940s 33.468us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 75.609us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 59.761us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.290s 228.209us 1 1 100.00
lc_ctrl_tl_intg_err 2.930s 918.162us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.930s 918.162us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.780s 831.101us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 971.846us 1 1 100.00
lc_ctrl_sec_cm 5.290s 228.209us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 971.846us 1 1 100.00
lc_ctrl_sec_cm 5.290s 228.209us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.770s 971.846us 1 1 100.00
lc_ctrl_sec_cm 5.290s 228.209us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.770s 971.846us 1 1 100.00
lc_ctrl_sec_cm 5.290s 228.209us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 971.846us 1 1 100.00
lc_ctrl_sec_cm 5.290s 228.209us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 971.846us 1 1 100.00
lc_ctrl_sec_cm 5.290s 228.209us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 971.846us 1 1 100.00
lc_ctrl_sec_cm 5.290s 228.209us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.770s 971.846us 1 1 100.00
lc_ctrl_sec_cm 5.290s 228.209us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.610s 1475.240us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.900s 288.466us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.570s 338.564us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.690s 431.572us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.690s 431.572us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.660s 272.146us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 12.390s 3810.991us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 12.390s 3810.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 33.880s 46197.883us 1 1 100.00