Simulation Results: lc_ctrl/volatile_unlock_enabled

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.43 %
  • code
  • 84.09 %
  • assert
  • 94.13 %
  • func
  • 93.06 %
  • line
  • 97.13 %
  • branch
  • 93.37 %
  • cond
  • 79.70 %
  • toggle
  • 85.75 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.350s 88.296us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.020s 21.427us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.790s 29.161us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.560s 101.385us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 51.363us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.030s 112.979us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.790s 29.161us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 51.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.250s 385.468us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.460s 1405.919us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.770s 39.386us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.240s 200.515us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.710s 169.658us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.190s 1452.449us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.710s 169.658us 1 1 100.00
lc_ctrl_prog_failure 2.240s 200.515us 1 1 100.00
lc_ctrl_errors 6.190s 1452.449us 1 1 100.00
lc_ctrl_security_escalation 7.490s 1072.629us 1 1 100.00
lc_ctrl_jtag_state_failure 33.140s 5622.686us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.250s 4773.996us 1 1 100.00
lc_ctrl_jtag_errors 12.600s 4106.381us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 4.830s 776.172us 1 1 100.00
lc_ctrl_jtag_state_post_trans 22.900s 1847.971us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.250s 4773.996us 1 1 100.00
lc_ctrl_jtag_errors 12.600s 4106.381us 0 1 0.00
lc_ctrl_jtag_access 5.200s 610.570us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.230s 3737.486us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.110s 72.803us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.320s 195.669us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.720s 2258.477us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 10.640s 6359.212us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.210s 41.683us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.930s 415.356us 1 1 100.00
lc_ctrl_jtag_alert_test 1.140s 232.463us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.990s 1505.688us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.100s 40.833us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 88.990s 8601.446us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.880s 56.769us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.480s 23.144us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.480s 23.144us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 21.427us 1 1 100.00
lc_ctrl_csr_rw 0.790s 29.161us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 51.363us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.950s 28.889us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 21.427us 1 1 100.00
lc_ctrl_csr_rw 0.790s 29.161us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 51.363us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.950s 28.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.370s 964.261us 1 1 100.00
lc_ctrl_tl_intg_err 3.640s 136.067us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.640s 136.067us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.460s 1405.919us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.710s 169.658us 1 1 100.00
lc_ctrl_sec_cm 6.370s 964.261us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.710s 169.658us 1 1 100.00
lc_ctrl_sec_cm 6.370s 964.261us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.710s 169.658us 1 1 100.00
lc_ctrl_sec_cm 6.370s 964.261us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.710s 169.658us 1 1 100.00
lc_ctrl_sec_cm 6.370s 964.261us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.710s 169.658us 1 1 100.00
lc_ctrl_sec_cm 6.370s 964.261us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.710s 169.658us 1 1 100.00
lc_ctrl_sec_cm 6.370s 964.261us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.710s 169.658us 1 1 100.00
lc_ctrl_sec_cm 6.370s 964.261us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.710s 169.658us 1 1 100.00
lc_ctrl_sec_cm 6.370s 964.261us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.490s 1072.629us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.250s 385.468us 1 1 100.00
lc_ctrl_jtag_state_post_trans 22.900s 1847.971us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.080s 316.062us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.080s 316.062us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.650s 2060.731us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.580s 763.349us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.580s 763.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 36.360s 11063.658us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 46320348746889618684350558994425459872360361719204293584485364673198287406702 2402
UVM_INFO @ 4106381302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---