Simulation Results: otbn

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.28 %
  • code
  • 95.31 %
  • assert
  • 90.43 %
  • func
  • 91.10 %
  • block
  • 99.41 %
  • line
  • 99.54 %
  • branch
  • 92.58 %
  • toggle
  • 91.55 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 45.940us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 30.039us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 14.652us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 16.904us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 23.766us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 23.795us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 62.196us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 16.904us 1 1 100.00
otbn_csr_aliasing 3.000s 23.795us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 125.000s 21174.614us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 26.000s 2993.202us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 25.000s 260.311us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 47.000s 337.812us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 99.000s 962.500us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 26.000s 454.389us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 22.000s 433.083us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 18.431us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 8.000s 29.787us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 73.148us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 36.884us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 57.261us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 57.261us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 14.652us 1 1 100.00
otbn_csr_rw 3.000s 16.904us 1 1 100.00
otbn_csr_aliasing 3.000s 23.795us 1 1 100.00
otbn_same_csr_outstanding 3.000s 17.045us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 14.652us 1 1 100.00
otbn_csr_rw 3.000s 16.904us 1 1 100.00
otbn_csr_aliasing 3.000s 23.795us 1 1 100.00
otbn_same_csr_outstanding 3.000s 17.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 70.779us 1 1 100.00
otbn_dmem_err 10.000s 78.907us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 8.000s 151.883us 0 1 0.00
otbn_controller_ispr_rdata_err 9.000s 214.608us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 68.729us 1 1 100.00
otbn_urnd_err 5.000s 17.506us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.334us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 18.597us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 48.259us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
otbn_tl_intg_err 3.000s 23.176us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 22.000s 115.698us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 45.940us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 10.000s 78.907us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 70.779us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
otbn_tl_intg_err 3.000s 23.176us 0 1 0.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 22.000s 433.083us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 70.779us 1 1 100.00
otbn_dmem_err 10.000s 78.907us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 18.431us 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.334us 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 30.039us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 70.779us 1 1 100.00
otbn_dmem_err 10.000s 78.907us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 18.431us 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.334us 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 22.000s 433.083us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 70.779us 1 1 100.00
otbn_dmem_err 10.000s 78.907us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 18.431us 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.334us 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 30.039us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 37.501us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 42.630us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 21.000s 103.749us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 21.000s 103.749us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 6.000s 23.883us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 60.669us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 7.000s 31.110us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 7.000s 31.110us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 26.309us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 30.039us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 30.039us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 30.039us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 99.000s 962.500us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 30.039us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 30.039us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 16.000s 540.705us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 30.039us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 263.000s 7527.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 34.000s 1207.163us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 77.835us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_alu_bignum_mod_err 83162068527599826748686698699664869397014962778653223253438621651343772291438 114
UVM_INFO @ 151882774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 14139482679885399982722811907095700154843743051764464999559536702604885708371 187
UVM_INFO @ 1207162552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 55372505551267378704022764398573434963891967632221862567176194336665195347494 119
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 31109785 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 31109785 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 31109785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: otbn_reg_block.status.status reset value: * 1 test run
otbn_tl_intg_err 47720497830871137769622862407506398586380809768945761202861244470145825270557 85
UVM_INFO @ 23176437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---