Simulation Results: otp_ctrl

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.03 %
  • code
  • 77.06 %
  • assert
  • 94.56 %
  • func
  • 71.46 %
  • line
  • 88.44 %
  • branch
  • 83.07 %
  • cond
  • 89.80 %
  • toggle
  • 82.34 %
  • FSM
  • 41.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.620s 52.018us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.200s 1502.679us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.860s 99.820us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.500s 44.667us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 2.850s 81.739us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.890s 249.300us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.720s 138.528us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.500s 44.667us 1 1 100.00
otp_ctrl_csr_aliasing 2.890s 249.300us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.160s 38.118us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.450s 556.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.640s 327.162us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.660s 125.088us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 20.720s 3872.178us 1 1 100.00
otp_ctrl_check_fail 11.420s 482.192us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.510s 308.783us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 33.420s 4729.956us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 25.430s 18014.107us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 22.470s 12930.689us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 19.460s 11545.147us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 16.630s 1070.295us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 30.380s 12428.479us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 138.770s 18800.286us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.270s 85.213us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.690s 181.362us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.190s 89.123us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.190s 89.123us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.860s 99.820us 1 1 100.00
otp_ctrl_csr_rw 1.500s 44.667us 1 1 100.00
otp_ctrl_csr_aliasing 2.890s 249.300us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.750s 89.083us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.860s 99.820us 1 1 100.00
otp_ctrl_csr_rw 1.500s 44.667us 1 1 100.00
otp_ctrl_csr_aliasing 2.890s 249.300us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.750s 89.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
otp_ctrl_tl_intg_err 6.680s 717.118us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 6.680s 717.118us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.200s 1502.679us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.200s 1502.679us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
otp_ctrl_macro_errs 16.630s 1070.295us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
otp_ctrl_macro_errs 16.630s 1070.295us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.130s 518.680us 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.660s 125.088us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 11.420s 482.192us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 33.420s 4729.956us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 33.420s 4729.956us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 33.420s 4729.956us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 33.420s 4729.956us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 33.420s 4729.956us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.200s 1502.679us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 33.420s 4729.956us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.200s 1502.679us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.750s 10977.084us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.510s 308.783us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.200s 1502.679us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.200s 1502.679us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 16.630s 1070.295us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 12.690s 8319.022us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 11.640s 6808.662us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 4 test runs
otp_ctrl_check_fail 91619246538298656173660211150661601018156357056642517876391983769974024546457 14170
UVM_INFO @ 482192030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 108755899551591598991681309918817514528815883420714657152931871184345714367372 17914
UVM_INFO @ 1070295469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65695913136403196871820856401822353326541094673785655448435687327799595442576 843
UVM_INFO @ 6808661742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 26538932562549321450552293018134200497685404293077253151381044884196403891511 114889
UVM_INFO @ 18800286362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---