Simulation Results: pattgen

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.59 %
  • code
  • 98.87 %
  • assert
  • 98.48 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 46.476us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 22.619us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 26.962us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 1445.199us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 61.245us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 105.410us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 26.962us 1 1 100.00
pattgen_csr_aliasing 2.000s 61.245us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 499.000s 89336.266us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 9.000s 1323.880us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 51.423us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 7530.000s 1372307.460us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 13.707us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 2.000s 15.314us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 1.000s 23.533us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 1.000s 23.533us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 22.619us 1 1 100.00
pattgen_csr_rw 1.000s 26.962us 1 1 100.00
pattgen_csr_aliasing 2.000s 61.245us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 21.670us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 22.619us 1 1 100.00
pattgen_csr_rw 1.000s 26.962us 1 1 100.00
pattgen_csr_aliasing 2.000s 61.245us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 21.670us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 193.385us 1 1 100.00
pattgen_sec_cm 1.000s 37.475us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 193.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 72.000s 3620.362us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 52.000s 10032.876us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) 1 test run
pattgen_inactive_level 56921443901316532544290936580325021980781549605471996354639062953046828706199 99
UVM_INFO @ 10032875878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 45973824875101436591019945262033470546121811900316657035212660274167812720852 154
UVM_ERROR @ 544492035 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 544492035 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 544554537 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]