Simulation Results: pwrmgr

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.90 %
  • code
  • 97.47 %
  • assert
  • 98.69 %
  • func
  • 97.53 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 96.46 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.790s 55.377us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.820s 24.397us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.790s 47.938us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.080s 194.034us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.940s 59.183us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.800s 73.808us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.790s 47.938us 1 1 100.00
pwrmgr_csr_aliasing 0.940s 59.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.920s 131.986us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.920s 131.986us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.730s 80.261us 1 1 100.00
pwrmgr_lowpower_invalid 0.740s 65.098us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 1.400s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.990s 219.498us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 1.400s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.180s 260.560us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.960s 261.580us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.770s 19.555us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.800s 38.284us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.690s 26.959us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 2.980s 334.577us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 2.980s 334.577us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.820s 24.397us 1 1 100.00
pwrmgr_csr_rw 0.790s 47.938us 1 1 100.00
pwrmgr_csr_aliasing 0.940s 59.183us 1 1 100.00
pwrmgr_same_csr_outstanding 1.160s 146.354us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.820s 24.397us 1 1 100.00
pwrmgr_csr_rw 0.790s 47.938us 1 1 100.00
pwrmgr_csr_aliasing 0.940s 59.183us 1 1 100.00
pwrmgr_same_csr_outstanding 1.160s 146.354us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.410s 114.628us 1 1 100.00
pwrmgr_sec_cm 1.310s 956.335us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.310s 956.335us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.310s 956.335us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.410s 114.628us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.800s 1369.057us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.180s 260.560us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.100s 200.850us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.600s 40.506us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.310s 956.335us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.310s 956.335us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.310s 956.335us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.640s 60.878us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.770s 51.773us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.970s 298.516us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.790s 47.938us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.790s 47.938us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 1.100s 369.258us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 6.070s 4457.446us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 112110730507697443718390415805497326631811257641718808348573467436533120855095 126
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 111414027196113833369454720911163061538746304426578330113310714915434040797235 79
UVM_ERROR @ 369258473 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 369258473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---