Simulation Results: rom_ctrl/64kb

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.97 %
  • code
  • 99.58 %
  • assert
  • 97.67 %
  • func
  • 96.66 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 10.200s 301.172us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.850s 1087.998us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.620s 291.131us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.500s 299.675us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.130s 370.162us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.090s 224.711us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.620s 291.131us 1 1 100.00
rom_ctrl_csr_aliasing 6.130s 370.162us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.170s 287.017us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 8.630s 298.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 9.730s 552.935us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 23.750s 9661.101us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 16.130s 563.093us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.280s 727.563us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.220s 516.093us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.220s 516.093us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.850s 1087.998us 1 1 100.00
rom_ctrl_csr_rw 7.620s 291.131us 1 1 100.00
rom_ctrl_csr_aliasing 6.130s 370.162us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.890s 222.319us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.850s 1087.998us 1 1 100.00
rom_ctrl_csr_rw 7.620s 291.131us 1 1 100.00
rom_ctrl_csr_aliasing 6.130s 370.162us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.890s 222.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 172.770s 10869.461us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.970s 1786.164us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 251.780s 1947.366us 1 1 100.00
rom_ctrl_tl_intg_err 60.490s 480.696us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 251.780s 1947.366us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 251.780s 1947.366us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 172.770s 10869.461us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 172.770s 10869.461us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 172.770s 10869.461us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 172.770s 10869.461us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 172.770s 10869.461us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 251.780s 1947.366us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 251.780s 1947.366us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 10.200s 301.172us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 10.200s 301.172us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 10.200s 301.172us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 60.490s 480.696us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 172.770s 10869.461us 1 1 100.00
rom_ctrl_kmac_err_chk 16.130s 563.093us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 172.770s 10869.461us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 172.770s 10869.461us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 172.770s 10869.461us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.970s 1786.164us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 251.780s 1947.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 206.110s 11536.515us 1 1 100.00