Simulation Results: rstmgr

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.70 %
  • code
  • 99.30 %
  • assert
  • 98.53 %
  • func
  • 95.27 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.68 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.320s 120.413us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.330s 156.785us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.200s 82.702us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.840s 488.703us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.950s 392.162us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.970s 100.697us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.200s 82.702us 1 1 100.00
rstmgr_csr_aliasing 2.950s 392.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.980s 188.000us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.180s 438.109us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.450s 226.908us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.750s 1572.587us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.750s 1572.587us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.750s 1572.587us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.750s 1572.587us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 5.140s 2075.932us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.050s 70.564us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.260s 321.775us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.260s 321.775us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.330s 156.785us 1 1 100.00
rstmgr_csr_rw 1.200s 82.702us 1 1 100.00
rstmgr_csr_aliasing 2.950s 392.162us 1 1 100.00
rstmgr_same_csr_outstanding 1.220s 88.904us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.330s 156.785us 1 1 100.00
rstmgr_csr_rw 1.200s 82.702us 1 1 100.00
rstmgr_csr_aliasing 2.950s 392.162us 1 1 100.00
rstmgr_same_csr_outstanding 1.220s 88.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.550s 16952.287us 1 1 100.00
rstmgr_tl_intg_err 1.900s 511.196us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.550s 16952.287us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.550s 16952.287us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.900s 511.196us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.230s 110.773us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.880s 1261.509us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.110s 304.243us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.550s 16952.287us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.200s 82.702us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.200s 82.702us 1 1 100.00