Simulation Results: rv_timer

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.48 %
  • code
  • 99.92 %
  • assert
  • 97.77 %
  • func
  • 76.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.69 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.690s 300.397us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.660s 19.494us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.580s 39.523us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.920s 141.828us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.960s 34.053us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.920s 65.764us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.580s 39.523us 1 1 100.00
rv_timer_csr_aliasing 0.960s 34.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.950s 415.704us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.150s 2700.209us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 61.460s 56775.497us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 61.460s 56775.497us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.810s 17550.381us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.650s 12.296us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.690s 13.531us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.490s 53.722us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.490s 53.722us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.660s 19.494us 1 1 100.00
rv_timer_csr_rw 0.580s 39.523us 1 1 100.00
rv_timer_csr_aliasing 0.960s 34.053us 1 1 100.00
rv_timer_same_csr_outstanding 0.700s 16.838us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.660s 19.494us 1 1 100.00
rv_timer_csr_rw 0.580s 39.523us 1 1 100.00
rv_timer_csr_aliasing 0.960s 34.053us 1 1 100.00
rv_timer_same_csr_outstanding 0.700s 16.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.770s 83.220us 1 1 100.00
rv_timer_tl_intg_err 1.340s 197.412us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.340s 197.412us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.690s 32.691us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.750s 46.304us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 6.830s 855.454us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 106130993966668439292485397470764328908291784463412941635108933558324472910826 75
UVM_INFO @ 46304084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 65405814641101787756711646139807389214389899008656060601280735002101353358823 75
UVM_INFO @ 415704042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
rv_timer_stress_all_with_rand_reset 38542351753652685493768342607801004605043960032000462407028685007155929646529 175
UVM_INFO @ 855454100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---