Simulation Results: spi_device/2p

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.11 %
  • code
  • 94.10 %
  • assert
  • 95.37 %
  • func
  • 74.85 %
  • line
  • 98.92 %
  • branch
  • 98.26 %
  • cond
  • 96.21 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 141.260s 40570.647us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.310s 172.767us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.950s 90.582us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 25.290s 7460.057us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.410s 1726.087us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.030s 547.297us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.950s 90.582us 1 1 100.00
spi_device_csr_aliasing 6.410s 1726.087us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.670s 30.497us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.160s 44.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.820s 21.551us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.490s 25.418us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.730s 44.815us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.810s 10.820us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.810s 10.820us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.840s 15458.145us 1 1 100.00
spi_device_tpm_sts_read 0.780s 70.195us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 17.820s 2489.392us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.870s 223.750us 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.710s 559.408us 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.710s 559.408us 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 14.270s 3830.054us 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 14.270s 3830.054us 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 14.270s 3830.054us 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 14.270s 3830.054us 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 14.270s 3830.054us 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.510s 1449.775us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.720s 4462.540us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.720s 4462.540us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.720s 4462.540us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 4.560s 526.052us 1 1 100.00
spi_device_read_buffer_direct 5.700s 426.043us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.720s 4462.540us 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 8.790s 1659.582us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 18.820s 2924.884us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 18.820s 2924.884us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 141.260s 40570.647us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 55.070s 20781.883us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 188.410s 225549.301us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.790s 51.458us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.080s 15.662us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.960s 518.363us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.960s 518.363us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.310s 172.767us 1 1 100.00
spi_device_csr_rw 1.950s 90.582us 1 1 100.00
spi_device_csr_aliasing 6.410s 1726.087us 1 1 100.00
spi_device_same_csr_outstanding 1.340s 59.851us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.310s 172.767us 1 1 100.00
spi_device_csr_rw 1.950s 90.582us 1 1 100.00
spi_device_csr_aliasing 6.410s 1726.087us 1 1 100.00
spi_device_same_csr_outstanding 1.340s 59.851us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.040s 109.657us 1 1 100.00
spi_device_tl_intg_err 7.370s 2098.579us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 7.370s 2098.579us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 85.510s 115952.659us 1 1 100.00