Simulation Results: spi_host

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.80 %
  • code
  • 94.90 %
  • assert
  • 95.27 %
  • func
  • 88.24 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 93.05 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 15.000s 1900.162us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 19.152us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 22.410us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 64.408us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 28.402us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 31.206us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 22.410us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.402us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 42.654us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 28.822us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 38.298us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 51.466us 1 1 100.00
spi_host_error_cmd 1.000s 60.244us 1 1 100.00
spi_host_event 4.000s 313.214us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 4.000s 604.781us 1 1 100.00
speed 1 1 100.00
spi_host_speed 4.000s 604.781us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 4.000s 604.781us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 162.791us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 33.246us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 4.000s 604.781us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 4.000s 604.781us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 15.000s 1900.162us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 15.000s 1900.162us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 49.000s 1502.867us 1 1 100.00
spien 1 1 100.00
spi_host_spien 265.000s 9617.780us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 70.000s 8148.813us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 70.471us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 51.466us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 119.780us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 17.180us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 93.030us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 93.030us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 19.152us 1 1 100.00
spi_host_csr_rw 1.000s 22.410us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.402us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 18.832us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 19.152us 1 1 100.00
spi_host_csr_rw 1.000s 22.410us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.402us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 18.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 165.431us 1 1 100.00
spi_host_sec_cm 1.000s 162.857us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 165.431us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
spi_host_upper_range_clkdiv 92.000s 200000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_upper_range_clkdiv 92131415538631688893671352540514985252534896660375965155154803404179946740482 115
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---