Simulation Results: sram_ctrl/ret

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.90 %
  • code
  • 83.09 %
  • assert
  • 97.80 %
  • func
  • 94.80 %
  • block
  • 93.39 %
  • line
  • 94.52 %
  • branch
  • 88.89 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 263.218us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 32.845us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.471us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 310.357us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.059us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 31.100us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 29.471us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.059us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.000s 3070.142us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 102.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 766.234us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 97.000s 3858.948us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 108.357us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 4.000s 148.899us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 889.849us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 501.504us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 66.016us 1 1 100.00
sram_ctrl_partial_access_b2b 287.000s 22279.556us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 134.830us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 36.446us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 51.973us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 169.578us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 128.181us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 25.000s 2066.327us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 28.929us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 250.830us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 250.830us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 32.845us 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.471us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.059us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 51.769us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 32.845us 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.471us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.059us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 51.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1549.903us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 2305.305us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 363.123us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 2305.305us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 363.123us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 169.578us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 169.578us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.471us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 501.504us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 501.504us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 501.504us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 889.849us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 79.188us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1549.903us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 37.793us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 263.218us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 263.218us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 501.504us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 2305.305us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 889.849us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 2305.305us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2305.305us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 263.218us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2305.305us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 72.000s 7719.174us 1 1 100.00