Simulation Results: sysrst_ctrl

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.58 %
  • code
  • 91.47 %
  • assert
  • 91.76 %
  • func
  • 58.50 %
  • line
  • 96.37 %
  • branch
  • 97.00 %
  • cond
  • 93.08 %
  • toggle
  • 99.77 %
  • FSM
  • 71.15 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.520s 2135.160us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.310s 2572.447us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.240s 2228.592us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.330s 2519.068us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 8.090s 4013.166us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.320s 2097.698us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 33.310s 39052.079us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.910s 3228.027us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.620s 2083.129us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.320s 2097.698us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.910s 3228.027us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 25.080s 28135.584us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 49.530s 44017.236us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 7.340s 3523.597us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.110s 4246.026us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.270s 2515.621us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.840s 2083.873us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 7.460s 3292.645us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.120s 2631.333us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 6.950s 3347.607us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 19.320s 30651.569us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 10.250s 10712.311us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.420s 2011.661us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 6.360s 2014.551us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.200s 2070.190us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.200s 2070.190us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.090s 4013.166us 1 1 100.00
sysrst_ctrl_csr_rw 2.320s 2097.698us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.910s 3228.027us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 19.260s 7675.281us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.090s 4013.166us 1 1 100.00
sysrst_ctrl_csr_rw 2.320s 2097.698us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.910s 3228.027us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 19.260s 7675.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 86.220s 42009.184us 1 1 100.00
sysrst_ctrl_tl_intg_err 21.760s 42871.802us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 21.760s 42871.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.300s 2970.695us 1 1 100.00