Simulation Results: uart

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.83 %
  • code
  • 95.84 %
  • assert
  • 97.98 %
  • func
  • 57.67 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.22 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.210s 622.622us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.940s 1070.521us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.610s 13.111us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.480s 1123.901us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.070s 159.269us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.140s 200.288us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.610s 13.111us 1 1 100.00
uart_csr_aliasing 1.070s 159.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 13.070s 12358.179us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.210s 622.622us 1 1 100.00
uart_tx_rx 13.070s 12358.179us 1 1 100.00
parity_error 2 2 100.00
uart_intr 9.920s 14788.174us 1 1 100.00
uart_rx_parity_err 64.260s 121223.278us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 13.070s 12358.179us 1 1 100.00
uart_intr 9.920s 14788.174us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 20.010s 160666.725us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 39.700s 30234.189us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 29.740s 25465.941us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 9.920s 14788.174us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 9.920s 14788.174us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 9.920s 14788.174us 1 1 100.00
perf 1 1 100.00
uart_perf 102.740s 9929.536us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.610s 1775.888us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.610s 1775.888us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.000s 1843.673us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.270s 2922.129us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 5.840s 8180.089us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.310s 5823.691us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 38.420s 24558.272us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 940.550s 282326.854us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.710s 14.031us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.730s 45.866us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.780s 202.107us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.780s 202.107us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.940s 1070.521us 1 1 100.00
uart_csr_rw 0.610s 13.111us 1 1 100.00
uart_csr_aliasing 1.070s 159.269us 1 1 100.00
uart_same_csr_outstanding 0.870s 28.442us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.940s 1070.521us 1 1 100.00
uart_csr_rw 0.610s 13.111us 1 1 100.00
uart_csr_aliasing 1.070s 159.269us 1 1 100.00
uart_same_csr_outstanding 0.870s 28.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.950s 45.423us 1 1 100.00
uart_tl_intg_err 1.120s 204.742us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.120s 204.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 50.090s 3863.133us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 72947422137549847574822930977217949948705447833582031668772475548400568907550 74
UVM_ERROR @ 77752706 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 259562706 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 259572706 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 259602706 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (40 [0x28] vs 183 [0xb7]) reg name: uart_reg_block.rdata