Simulation Results: adc_ctrl

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.68 %
  • code
  • 92.16 %
  • assert
  • 91.90 %
  • func
  • 12.97 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 85.65 %
  • toggle
  • 99.76 %
  • FSM
  • 81.08 %
Validation stages
unmapped
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 15 25 60.00
adc_ctrl_smoke 3.630s 5898.008us 1 1 100.00
adc_ctrl_filters_polled 1.490s 521.645us 0 1 0.00
adc_ctrl_filters_polled_fixed 0.800s 389.181us 0 1 0.00
adc_ctrl_filters_interrupt 1.700s 449.800us 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.960s 434.518us 0 1 0.00
adc_ctrl_filters_wakeup 1.530s 522.258us 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.830s 406.474us 0 1 0.00
adc_ctrl_clock_gating 1.380s 403.618us 0 1 0.00
adc_ctrl_filters_both 1.670s 339.506us 0 1 0.00
adc_ctrl_poweron_counter 8.140s 3985.089us 1 1 100.00
adc_ctrl_lowpower_counter 26.760s 46189.859us 1 1 100.00
adc_ctrl_fsm_reset 150.240s 98793.112us 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 1.860s 3026.411us 0 1 0.00
adc_ctrl_stress_all 1.310s 812.237us 0 1 0.00
adc_ctrl_sec_cm 4.220s 7812.229us 1 1 100.00
adc_ctrl_tl_errors 2.120s 439.831us 1 1 100.00
adc_ctrl_tl_intg_err 15.440s 8343.046us 1 1 100.00
adc_ctrl_intr_test 0.960s 319.368us 1 1 100.00
adc_ctrl_alert_test 0.790s 497.751us 1 1 100.00
adc_ctrl_csr_hw_reset 1.840s 1151.448us 1 1 100.00
adc_ctrl_csr_rw 2.260s 491.812us 1 1 100.00
adc_ctrl_csr_bit_bash 59.750s 26369.377us 1 1 100.00
adc_ctrl_csr_aliasing 1.830s 799.687us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.440s 2359.101us 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.090s 491.452us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 32152897419515457325500419773143347462535324947410040379278287777683333623458 388
UVM_INFO @ 521645208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 4111983884340714843942100913329254296941898481351634060727594368836189816844 388
UVM_INFO @ 389181246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 55123733323337026805237427823099967084327697273430772168976819513903382484520 388
UVM_INFO @ 449799661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 7116262543838480217579057507341188328148247892035846604457270725076711955663 388
UVM_INFO @ 434517863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 4904902271745568539443107767615287723217626250427445397045596942655128653437 388
UVM_INFO @ 522258444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 22431530520066737883321014704969071372154513314604165694181279726004595195078 388
UVM_INFO @ 406474484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 48309212809597549859330365891884565256977318399906776106388242989827589391209 388
UVM_INFO @ 403617927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 91206739210428189707452184517600345012680293243812374442443772067661474850303 388
UVM_INFO @ 339505570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 61717986418690055921349456497115767512700244758070593012532606724747781575263 416
UVM_INFO @ 3026410701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 77689234099090901710381383741273759659218993874165265867043499005073738424211 389
UVM_INFO @ 812236965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---