| unmapped |
|
96.88% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 31 | 32 | 96.88 | |||
| aes_wake_up | 2.000s | 108.537us | 1 | 1 | 100.00 | |
| aes_nist_vectors | 9.000s | 392.252us | 1 | 1 | 100.00 | |
| aes_deinit | 2.000s | 84.556us | 1 | 1 | 100.00 | |
| aes_man_cfg_err | 2.000s | 76.687us | 1 | 1 | 100.00 | |
| aes_readability | 4.000s | 629.340us | 1 | 1 | 100.00 | |
| aes_smoke | 2.000s | 57.784us | 1 | 1 | 100.00 | |
| aes_config_error | 4.000s | 150.493us | 1 | 1 | 100.00 | |
| aes_stress | 4.000s | 80.766us | 1 | 1 | 100.00 | |
| aes_b2b | 8.000s | 255.505us | 1 | 1 | 100.00 | |
| aes_clear | 2.000s | 208.627us | 1 | 1 | 100.00 | |
| aes_alert_reset | 3.000s | 112.897us | 1 | 1 | 100.00 | |
| aes_sideload | 4.000s | 262.330us | 1 | 1 | 100.00 | |
| aes_reseed | 3.000s | 269.012us | 1 | 1 | 100.00 | |
| aes_fi | 3.000s | 237.682us | 1 | 1 | 100.00 | |
| aes_control_fi | 2.000s | 48.913us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 3.000s | 79.825us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 3.000s | 52.985us | 1 | 1 | 100.00 | |
| aes_core_fi | 4.000s | 70.154us | 1 | 1 | 100.00 | |
| aes_stress_all | 9.000s | 254.543us | 1 | 1 | 100.00 | |
| aes_stress_all_with_rand_reset | 12.000s | 419.009us | 0 | 1 | 0.00 | |
| aes_sec_cm | 3.000s | 619.776us | 1 | 1 | 100.00 | |
| aes_tl_errors | 3.000s | 204.486us | 1 | 1 | 100.00 | |
| aes_tl_intg_err | 2.000s | 207.517us | 1 | 1 | 100.00 | |
| aes_shadow_reg_errors | 2.000s | 159.558us | 1 | 1 | 100.00 | |
| aes_shadow_reg_errors_with_csr_rw | 3.000s | 106.794us | 1 | 1 | 100.00 | |
| aes_csr_hw_reset | 3.000s | 148.330us | 1 | 1 | 100.00 | |
| aes_csr_rw | 1.000s | 58.122us | 1 | 1 | 100.00 | |
| aes_csr_bit_bash | 4.000s | 123.421us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 3.000s | 1558.082us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 134.863us | 1 | 1 | 100.00 | |
| aes_csr_mem_rw_with_rand_reset | 1.000s | 68.458us | 1 | 1 | 100.00 | |
| aes_alert_test | 2.000s | 112.519us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1287) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| aes_stress_all_with_rand_reset | 102654413219855243388784281512851903700541279842704231278258658083928115911281 | 415 |
UVM_INFO @ 419008610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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