Simulation Results: aes/unmasked

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.83 %
  • code
  • 89.74 %
  • assert
  • 97.73 %
  • func
  • 76.02 %
  • block
  • 89.72 %
  • line
  • 92.07 %
  • branch
  • 80.10 %
  • toggle
  • 97.90 %
  • FSM
  • 88.89 %
Validation stages
unmapped
96.88%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 31 32 96.88
aes_wake_up 1.000s 57.465us 1 1 100.00
aes_nist_vectors 4.000s 349.785us 1 1 100.00
aes_deinit 2.000s 251.754us 1 1 100.00
aes_man_cfg_err 1.000s 75.969us 1 1 100.00
aes_readability 2.000s 53.685us 1 1 100.00
aes_smoke 1.000s 62.225us 1 1 100.00
aes_config_error 2.000s 121.458us 1 1 100.00
aes_stress 2.000s 94.378us 1 1 100.00
aes_b2b 5.000s 211.229us 1 1 100.00
aes_clear 2.000s 115.742us 1 1 100.00
aes_alert_reset 2.000s 108.734us 1 1 100.00
aes_sideload 3.000s 656.660us 1 1 100.00
aes_reseed 3.000s 97.591us 1 1 100.00
aes_fi 2.000s 102.912us 1 1 100.00
aes_control_fi 3.000s 59.333us 1 1 100.00
aes_cipher_fi 2.000s 51.751us 1 1 100.00
aes_ctr_fi 3.000s 73.107us 1 1 100.00
aes_core_fi 2.000s 101.194us 1 1 100.00
aes_stress_all 16.000s 1166.197us 1 1 100.00
aes_stress_all_with_rand_reset 15.000s 1166.769us 0 1 0.00
aes_sec_cm 2.000s 532.754us 1 1 100.00
aes_tl_errors 2.000s 88.059us 1 1 100.00
aes_tl_intg_err 2.000s 129.307us 1 1 100.00
aes_shadow_reg_errors 3.000s 677.119us 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 313.566us 1 1 100.00
aes_csr_hw_reset 2.000s 104.416us 1 1 100.00
aes_csr_rw 1.000s 74.330us 1 1 100.00
aes_csr_bit_bash 3.000s 361.610us 1 1 100.00
aes_csr_aliasing 2.000s 99.615us 1 1 100.00
aes_same_csr_outstanding 2.000s 461.106us 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 92.415us 1 1 100.00
aes_alert_test 2.000s 78.673us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 49073046868660888889191053838359178506328834992984223919570969174659164025081 976
UVM_INFO @ 1166769414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---