Simulation Results: alert_handler

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.22 %
  • code
  • 92.24 %
  • assert
  • 98.23 %
  • func
  • 83.20 %
  • line
  • 99.71 %
  • branch
  • 98.42 %
  • cond
  • 91.65 %
  • toggle
  • 92.37 %
  • FSM
  • 79.03 %
Validation stages
unmapped
92.31%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 24 26 92.31
alert_handler_smoke 16.770s 296.863us 1 1 100.00
alert_handler_random_alerts 3.440s 206.626us 1 1 100.00
alert_handler_random_classes 17.070s 627.146us 1 1 100.00
alert_handler_esc_intr_timeout 14.690s 482.673us 1 1 100.00
alert_handler_esc_alert_accum 15.850s 270.982us 1 1 100.00
alert_handler_sig_int_fail 18.780s 2110.922us 1 1 100.00
alert_handler_entropy 2273.030s 217480.181us 1 1 100.00
alert_handler_ping_timeout 277.190s 45560.246us 0 1 0.00
alert_handler_lpg 1655.000s 48304.467us 1 1 100.00
alert_handler_lpg_stub_clk 668.170s 9232.112us 1 1 100.00
alert_handler_entropy_stress 6.760s 770.123us 0 1 0.00
alert_handler_stress_all 2624.470s 75237.890us 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 345.020s 17275.359us 1 1 100.00
alert_handler_alert_accum_saturation 2.840s 271.998us 1 1 100.00
alert_handler_stress_all_with_rand_reset 180.920s 2869.199us 1 1 100.00
alert_handler_sec_cm 9.530s 250.749us 1 1 100.00
alert_handler_shadow_reg_errors 61.040s 1137.312us 1 1 100.00
alert_handler_tl_errors 2.640s 43.532us 1 1 100.00
alert_handler_tl_intg_err 46.540s 1274.104us 1 1 100.00
alert_handler_intr_test 1.240s 10.517us 1 1 100.00
alert_handler_csr_hw_reset 5.990s 428.871us 1 1 100.00
alert_handler_csr_rw 3.840s 33.209us 1 1 100.00
alert_handler_csr_bit_bash 117.410s 1670.026us 1 1 100.00
alert_handler_csr_aliasing 35.730s 1626.421us 1 1 100.00
alert_handler_same_csr_outstanding 12.560s 1459.622us 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.010s 73.022us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 23206312746033141465577371899293858072661121817453817630806445109578735137732 153
UVM_INFO @ 45560245607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 68411139655646705012081165353723467126990633924702091966245978028233615478258 186
UVM_INFO @ 770122525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---