| unmapped |
|
95.24% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 20 | 21 | 95.24 | |||
| edn_smoke | 0.780s | 26.945us | 1 | 1 | 100.00 | |
| edn_regwen | 0.920s | 63.028us | 1 | 1 | 100.00 | |
| edn_genbits | 1.200s | 73.103us | 1 | 1 | 100.00 | |
| edn_stress_all | 3.830s | 250.534us | 1 | 1 | 100.00 | |
| edn_stress_all_with_rand_reset | 136.160s | 12125.258us | 0 | 1 | 0.00 | |
| edn_intr | 1.280s | 23.278us | 1 | 1 | 100.00 | |
| edn_alert | 1.070s | 41.641us | 1 | 1 | 100.00 | |
| edn_err | 0.860s | 28.777us | 1 | 1 | 100.00 | |
| edn_disable | 0.780s | 39.689us | 1 | 1 | 100.00 | |
| edn_disable_auto_req_mode | 0.990s | 210.027us | 1 | 1 | 100.00 | |
| edn_sec_cm | 6.700s | 1756.566us | 1 | 1 | 100.00 | |
| edn_tl_errors | 1.150s | 75.282us | 1 | 1 | 100.00 | |
| edn_tl_intg_err | 1.320s | 211.648us | 1 | 1 | 100.00 | |
| edn_alert_test | 1.140s | 35.012us | 1 | 1 | 100.00 | |
| edn_intr_test | 0.820s | 28.968us | 1 | 1 | 100.00 | |
| edn_csr_hw_reset | 0.810s | 17.375us | 1 | 1 | 100.00 | |
| edn_csr_rw | 0.840s | 54.296us | 1 | 1 | 100.00 | |
| edn_csr_bit_bash | 2.440s | 58.598us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 1.360s | 53.197us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 0.980s | 46.580us | 1 | 1 | 100.00 | |
| edn_csr_mem_rw_with_rand_reset | 1.590s | 31.920us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! | 1 test run | |||
| edn_stress_all_with_rand_reset | 15478887850898219605741308302264413297237324827040442236166684621135815778226 | 265 |
UVM_INFO @ 12125257943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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