| unmapped |
|
95.24% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 20 | 21 | 95.24 | |||
| edn_smoke | 0.870s | 54.712us | 1 | 1 | 100.00 | |
| edn_regwen | 0.730s | 58.843us | 1 | 1 | 100.00 | |
| edn_genbits | 2.030s | 247.053us | 1 | 1 | 100.00 | |
| edn_stress_all | 2.820s | 451.480us | 1 | 1 | 100.00 | |
| edn_stress_all_with_rand_reset | 50.840s | 3752.377us | 0 | 1 | 0.00 | |
| edn_intr | 0.740s | 32.486us | 1 | 1 | 100.00 | |
| edn_alert | 1.030s | 42.841us | 1 | 1 | 100.00 | |
| edn_err | 0.890s | 50.592us | 1 | 1 | 100.00 | |
| edn_disable | 0.720s | 39.280us | 1 | 1 | 100.00 | |
| edn_disable_auto_req_mode | 0.960s | 148.824us | 1 | 1 | 100.00 | |
| edn_sec_cm | 2.220s | 195.650us | 1 | 1 | 100.00 | |
| edn_tl_errors | 1.730s | 108.085us | 1 | 1 | 100.00 | |
| edn_tl_intg_err | 2.040s | 564.555us | 1 | 1 | 100.00 | |
| edn_alert_test | 0.900s | 22.544us | 1 | 1 | 100.00 | |
| edn_intr_test | 0.770s | 24.068us | 1 | 1 | 100.00 | |
| edn_csr_hw_reset | 0.800s | 26.919us | 1 | 1 | 100.00 | |
| edn_csr_rw | 0.790s | 14.306us | 1 | 1 | 100.00 | |
| edn_csr_bit_bash | 1.520s | 136.819us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 1.210s | 143.025us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 1.060s | 122.916us | 1 | 1 | 100.00 | |
| edn_csr_mem_rw_with_rand_reset | 0.980s | 26.605us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| edn_stress_all_with_rand_reset | 102234146364984580113249057902728549635168434109029953903584295618520411410070 | 273 |
UVM_INFO @ 3752377025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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