Simulation Results: hmac

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.77 %
  • code
  • 97.96 %
  • assert
  • 98.02 %
  • func
  • 43.32 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 28 28 100.00
hmac_smoke 7.750s 3793.920us 1 1 100.00
hmac_long_msg 13.560s 1333.607us 1 1 100.00
hmac_stress_reset 1.900s 174.621us 1 1 100.00
hmac_back_pressure 24.520s 524.202us 1 1 100.00
hmac_datapath_stress 106.240s 10792.019us 1 1 100.00
hmac_burst_wr 1.820s 625.141us 1 1 100.00
hmac_error 38.750s 868.737us 1 1 100.00
hmac_wipe_secret 9.110s 3556.829us 1 1 100.00
hmac_test_sha256_vectors 199.710s 48578.157us 1 1 100.00
hmac_test_sha384_vectors 20.360s 512.476us 1 1 100.00
hmac_test_sha512_vectors 21.300s 1123.659us 1 1 100.00
hmac_test_hmac256_vectors 6.890s 831.505us 1 1 100.00
hmac_test_hmac384_vectors 10.430s 1685.359us 1 1 100.00
hmac_test_hmac512_vectors 10.710s 311.519us 1 1 100.00
hmac_stress_all 1591.150s 256695.857us 1 1 100.00
hmac_stress_all_with_rand_reset 22.060s 630.449us 1 1 100.00
hmac_directed 1.040s 29.794us 1 1 100.00
hmac_sec_cm 0.980s 101.901us 1 1 100.00
hmac_tl_errors 2.490s 53.376us 1 1 100.00
hmac_tl_intg_err 3.160s 759.798us 1 1 100.00
hmac_intr_test 0.620s 32.091us 1 1 100.00
hmac_alert_test 0.650s 23.515us 1 1 100.00
hmac_csr_hw_reset 1.010s 119.007us 1 1 100.00
hmac_csr_rw 0.780s 15.247us 1 1 100.00
hmac_csr_bit_bash 12.990s 3704.568us 1 1 100.00
hmac_csr_aliasing 3.600s 122.667us 1 1 100.00
hmac_same_csr_outstanding 1.510s 52.842us 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.690s 40.365us 1 1 100.00