Simulation Results: i2c

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.17 %
  • code
  • 81.40 %
  • assert
  • 96.19 %
  • func
  • 77.91 %
  • line
  • 96.41 %
  • branch
  • 92.33 %
  • cond
  • 84.78 %
  • toggle
  • 89.45 %
  • FSM
  • 44.05 %
Validation stages
unmapped
86.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 43 50 86.00
i2c_host_smoke 40.150s 9163.370us 1 1 100.00
i2c_host_override 0.670s 18.693us 1 1 100.00
i2c_host_fifo_watermark 112.610s 3058.911us 1 1 100.00
i2c_host_fifo_overflow 21.150s 4198.704us 1 1 100.00
i2c_host_fifo_reset_fmt 0.990s 138.313us 1 1 100.00
i2c_host_fifo_fmt_empty 15.410s 1867.700us 1 1 100.00
i2c_host_fifo_reset_rx 4.230s 516.022us 1 1 100.00
i2c_host_fifo_full 40.520s 40153.384us 1 1 100.00
i2c_host_perf 617.760s 72655.920us 1 1 100.00
i2c_host_perf_precise 65.280s 2360.121us 1 1 100.00
i2c_host_stretch_timeout 5.700s 498.360us 1 1 100.00
i2c_host_error_intr 0.730s 15.631us 0 1 0.00
i2c_host_stress_all 3600.185s 0.000us 0 1 0.00
i2c_target_glitch 1.870s 2011.437us 0 1 0.00
i2c_target_smoke 5.000s 617.370us 1 1 100.00
i2c_target_stress_wr 5.240s 10819.816us 1 1 100.00
i2c_target_stress_rd 48.270s 6112.386us 1 1 100.00
i2c_target_stretch 2.820s 1417.736us 1 1 100.00
i2c_target_intr_smoke 3.590s 733.429us 1 1 100.00
i2c_target_intr_stress_wr 49.180s 11860.507us 1 1 100.00
i2c_target_timeout 5.760s 7993.876us 1 1 100.00
i2c_target_unexp_stop 1.600s 1616.096us 0 1 0.00
i2c_target_fifo_reset_acq 1.110s 189.088us 1 1 100.00
i2c_target_fifo_reset_tx 1.500s 176.440us 1 1 100.00
i2c_target_perf 2.950s 611.401us 1 1 100.00
i2c_target_stress_all 235.510s 46336.601us 1 1 100.00
i2c_target_bad_addr 3.540s 719.908us 1 1 100.00
i2c_target_hrst 1.800s 320.918us 1 1 100.00
i2c_host_stress_all_with_rand_reset 39.970s 3814.719us 0 1 0.00
i2c_target_stress_all_with_rand_reset 0.920s 102.583us 0 1 0.00
i2c_host_mode_toggle 0.680s 63.452us 0 1 0.00
i2c_host_may_nack 12.160s 409.935us 1 1 100.00
i2c_target_fifo_watermarks_acq 3.100s 1025.904us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.020s 99.256us 1 1 100.00
i2c_target_tx_stretch_ctrl 3.330s 263.195us 1 1 100.00
i2c_target_smbus_maxlen 1.460s 1411.975us 1 1 100.00
i2c_target_nack_acqfull 2.000s 624.907us 1 1 100.00
i2c_target_nack_acqfull_addr 2.350s 11780.783us 1 1 100.00
i2c_target_nack_txstretch 1.610s 308.762us 1 1 100.00
i2c_tl_errors 1.710s 1028.749us 1 1 100.00
i2c_tl_intg_err 1.220s 244.995us 1 1 100.00
i2c_sec_cm 0.980s 274.748us 1 1 100.00
i2c_intr_test 0.710s 16.729us 1 1 100.00
i2c_alert_test 0.720s 21.843us 1 1 100.00
i2c_csr_hw_reset 0.840s 78.393us 1 1 100.00
i2c_csr_rw 0.710s 67.826us 1 1 100.00
i2c_csr_bit_bash 2.190s 63.409us 1 1 100.00
i2c_csr_aliasing 2.000s 106.566us 1 1 100.00
i2c_same_csr_outstanding 0.810s 124.408us 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.830s 94.662us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 3 test runs
i2c_host_error_intr 82350510502706668412524408405477126087546398900233057510565459628201449450114 80
UVM_INFO @ 15631375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 125321514817900235801494585702331644546944108055195665472593261169133865858 85
UVM_INFO @ 102583341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 19433322141029546689750081726487887425986813444298391156807736093574297641631 81
UVM_INFO @ 63452496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
i2c_host_stress_all 69326110122545195086047123557027730471707134007736984809544917081319542191786 None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 84411769052427135877705628508080952669244633945345809147716307336677950504248 84
UVM_INFO @ 2011437300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 73812637459587612421448066346319994008981492514888950947012454427941362854501 78
UVM_INFO @ 1616095527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 103153572534604339454807693371046703815955846799641365189756638365018678750298 95
UVM_INFO @ 3814718674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---