Simulation Results: lc_ctrl/volatile_unlock_disabled

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.79 %
  • code
  • 83.43 %
  • assert
  • 94.13 %
  • func
  • 91.81 %
  • line
  • 97.01 %
  • branch
  • 93.27 %
  • cond
  • 79.24 %
  • toggle
  • 85.95 %
  • FSM
  • 61.68 %
Validation stages
unmapped
94.87%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 37 39 94.87
lc_ctrl_smoke 1.880s 298.191us 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.160s 36.415us 1 1 100.00
lc_ctrl_state_failure 9.070s 357.013us 1 1 100.00
lc_ctrl_state_post_trans 2.140s 681.655us 1 1 100.00
lc_ctrl_prog_failure 2.560s 546.674us 1 1 100.00
lc_ctrl_errors 6.370s 427.461us 1 1 100.00
lc_ctrl_security_escalation 6.580s 263.436us 1 1 100.00
lc_ctrl_regwen_during_op 5.980s 367.691us 1 1 100.00
lc_ctrl_claim_transition_if 0.940s 20.239us 1 1 100.00
lc_ctrl_jtag_smoke 4.980s 184.931us 1 1 100.00
lc_ctrl_jtag_state_failure 19.030s 1381.813us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.040s 1995.132us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.480s 1225.219us 1 1 100.00
lc_ctrl_jtag_errors 19.240s 2244.742us 1 1 100.00
lc_ctrl_jtag_access 4.230s 1142.457us 1 1 100.00
lc_ctrl_jtag_priority 6.720s 472.651us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 27.550s 5791.702us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.810s 446.955us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.470s 38.656us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.960s 472.061us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.780s 670.317us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.630s 92.423us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.390s 65.555us 1 1 100.00
lc_ctrl_jtag_alert_test 1.290s 44.286us 1 1 100.00
lc_ctrl_sec_mubi 7.090s 625.247us 1 1 100.00
lc_ctrl_sec_token_mux 5.100s 771.066us 1 1 100.00
lc_ctrl_sec_token_digest 4.460s 3186.327us 1 1 100.00
lc_ctrl_stress_all 6.460s 317.224us 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 56.820s 17460.821us 0 1 0.00
lc_ctrl_sec_cm 6.160s 564.420us 1 1 100.00
lc_ctrl_tl_errors 1.680s 215.113us 1 1 100.00
lc_ctrl_tl_intg_err 2.020s 67.395us 1 1 100.00
lc_ctrl_alert_test 1.680s 26.467us 1 1 100.00
lc_ctrl_csr_hw_reset 1.090s 22.664us 1 1 100.00
lc_ctrl_csr_rw 1.150s 13.728us 1 1 100.00
lc_ctrl_csr_bit_bash 2.050s 107.192us 1 1 100.00
lc_ctrl_csr_aliasing 1.530s 18.344us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.590s 42.653us 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.480s 19.424us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 85228632756421216293814103733193481966721317428640725324360120344154002243194 3420
UVM_INFO @ 317224221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 82562777675634655882206011935566722103660948366121905774632055471465273049962 20552
UVM_INFO @ 17460820624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---