Simulation Results: lc_ctrl/volatile_unlock_enabled

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.83 %
  • code
  • 84.25 %
  • assert
  • 94.83 %
  • func
  • 93.42 %
  • line
  • 97.13 %
  • branch
  • 93.66 %
  • cond
  • 79.63 %
  • toggle
  • 87.26 %
  • FSM
  • 63.55 %
Validation stages
unmapped
97.44%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 38 39 97.44
lc_ctrl_smoke 1.740s 25.105us 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.040s 15.650us 1 1 100.00
lc_ctrl_state_failure 7.560s 1349.205us 1 1 100.00
lc_ctrl_state_post_trans 6.960s 758.314us 1 1 100.00
lc_ctrl_prog_failure 2.320s 61.028us 1 1 100.00
lc_ctrl_errors 6.720s 388.165us 1 1 100.00
lc_ctrl_security_escalation 5.550s 1186.515us 1 1 100.00
lc_ctrl_regwen_during_op 17.910s 818.242us 1 1 100.00
lc_ctrl_claim_transition_if 0.890s 70.095us 1 1 100.00
lc_ctrl_jtag_smoke 9.130s 1004.146us 1 1 100.00
lc_ctrl_jtag_state_failure 25.710s 2127.466us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.170s 3049.988us 1 1 100.00
lc_ctrl_jtag_prog_failure 17.600s 4938.138us 1 1 100.00
lc_ctrl_jtag_errors 18.850s 5314.473us 1 1 100.00
lc_ctrl_jtag_access 7.410s 1398.366us 1 1 100.00
lc_ctrl_jtag_priority 4.440s 197.603us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.040s 502.062us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.430s 235.131us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.500s 56.828us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.770s 2387.111us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.070s 1579.545us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.450s 22.469us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.590s 368.939us 1 1 100.00
lc_ctrl_jtag_alert_test 1.130s 108.980us 1 1 100.00
lc_ctrl_sec_mubi 7.610s 1259.978us 1 1 100.00
lc_ctrl_sec_token_mux 8.480s 327.081us 1 1 100.00
lc_ctrl_sec_token_digest 9.600s 8394.975us 1 1 100.00
lc_ctrl_stress_all 50.270s 18814.580us 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 28.640s 8688.182us 0 1 0.00
lc_ctrl_sec_cm 7.320s 295.712us 1 1 100.00
lc_ctrl_tl_errors 3.180s 144.693us 1 1 100.00
lc_ctrl_tl_intg_err 2.170s 1732.665us 1 1 100.00
lc_ctrl_alert_test 0.780s 222.528us 1 1 100.00
lc_ctrl_csr_hw_reset 1.050s 59.647us 1 1 100.00
lc_ctrl_csr_rw 0.890s 16.571us 1 1 100.00
lc_ctrl_csr_bit_bash 1.100s 36.687us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 71.193us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.370s 32.610us 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.340s 109.598us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 72629155158655483941271153285827335436625075257566920398117585021910394862453 3018
UVM_INFO @ 8688181510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---