Simulation Results: otbn

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.90 %
  • code
  • 94.34 %
  • assert
  • 90.33 %
  • func
  • 97.03 %
  • block
  • 99.36 %
  • line
  • 99.49 %
  • branch
  • 92.10 %
  • toggle
  • 88.22 %
  • FSM
  • 97.56 %
Validation stages
unmapped
95.24%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 40 42 95.24
otbn_smoke 10.000s 206.323us 1 1 100.00
otbn_smoke_vectorized 7.000s 23.701us 1 1 100.00
otbn_single 13.000s 56.934us 1 1 100.00
otbn_multi 16.000s 56.441us 1 1 100.00
otbn_reset 28.000s 313.546us 1 1 100.00
otbn_multi_err 18.000s 86.682us 0 1 0.00
otbn_imem_err 8.000s 19.274us 1 1 100.00
otbn_dmem_err 26.000s 48.202us 1 1 100.00
otbn_escalate 20.000s 39.638us 1 1 100.00
otbn_alu_bignum_mod_err 38.000s 29.421us 1 1 100.00
otbn_controller_ispr_rdata_err 41.000s 141.804us 1 1 100.00
otbn_mac_bignum_acc_err 13.000s 53.722us 0 1 0.00
otbn_rf_bignum_intg_err 7.000s 104.356us 1 1 100.00
otbn_rf_base_intg_err 9.000s 199.201us 1 1 100.00
otbn_stress_all 115.000s 1328.610us 1 1 100.00
otbn_stress_all_with_rand_reset 456.000s 16548.362us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 10.729us 1 1 100.00
otbn_illegal_mem_acc 14.000s 35.942us 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 29.358us 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 31.525us 1 1 100.00
otbn_rnd_sec_cm 23.000s 310.102us 1 1 100.00
otbn_ctrl_redun 32.000s 13.331us 1 1 100.00
otbn_sec_wipe_err 5.000s 10.250us 1 1 100.00
otbn_urnd_err 7.000s 25.128us 1 1 100.00
otbn_sw_no_acc 9.000s 20.729us 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 45.461us 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 46.623us 1 1 100.00
otbn_partial_wipe 5.000s 37.935us 1 1 100.00
otbn_passthru_mem_tl_intg_err 35.000s 159.431us 1 1 100.00
otbn_sec_cm 218.000s 4991.112us 1 1 100.00
otbn_tl_errors 6.000s 414.500us 1 1 100.00
otbn_tl_intg_err 11.000s 65.450us 1 1 100.00
otbn_intr_test 4.000s 16.375us 1 1 100.00
otbn_alert_test 35.000s 87.702us 1 1 100.00
otbn_mem_walk 32.000s 3121.133us 1 1 100.00
otbn_mem_partial_access 14.000s 753.430us 1 1 100.00
otbn_csr_hw_reset 34.000s 45.570us 1 1 100.00
otbn_csr_rw 33.000s 52.724us 1 1 100.00
otbn_csr_bit_bash 35.000s 123.721us 1 1 100.00
otbn_csr_aliasing 34.000s 15.675us 1 1 100.00
otbn_same_csr_outstanding 5.000s 51.047us 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 33.000s 49.330us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 8533950535527230271184498816432035688871670922960249384409818592860393447995 257
UVM_INFO @ 86682072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_mac_bignum_acc_err 102851189553544631026129962908899731442148111339448258476092296298984056725846 114
UVM_INFO @ 53721754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---