Simulation Results: rom_ctrl/32kb

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.13 %
  • code
  • 99.11 %
  • assert
  • 97.67 %
  • func
  • 97.61 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 97.77 %
  • toggle
  • 99.77 %
  • FSM
  • 100.00 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rom_ctrl_smoke 5.640s 3891.227us 1 1 100.00
rom_ctrl_stress_all 11.160s 878.156us 1 1 100.00
rom_ctrl_max_throughput_chk 4.060s 353.142us 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.210s 1567.927us 1 1 100.00
rom_ctrl_kmac_err_chk 8.780s 309.170us 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 267.620s 12269.185us 1 1 100.00
rom_ctrl_sec_cm 105.720s 1684.544us 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.270s 1162.862us 1 1 100.00
rom_ctrl_tl_errors 7.810s 1333.424us 1 1 100.00
rom_ctrl_tl_intg_err 42.910s 958.549us 1 1 100.00
rom_ctrl_alert_test 4.910s 2184.375us 1 1 100.00
rom_ctrl_mem_walk 3.760s 386.529us 1 1 100.00
rom_ctrl_mem_partial_access 3.230s 371.051us 1 1 100.00
rom_ctrl_csr_hw_reset 5.890s 167.428us 1 1 100.00
rom_ctrl_csr_rw 4.180s 692.405us 1 1 100.00
rom_ctrl_csr_bit_bash 3.770s 124.550us 1 1 100.00
rom_ctrl_csr_aliasing 3.530s 206.862us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.750s 126.011us 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.500s 334.518us 1 1 100.00