Simulation Results: rom_ctrl/64kb

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.47 %
  • code
  • 97.85 %
  • assert
  • 97.67 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.62 %
  • toggle
  • 99.59 %
  • FSM
  • 93.33 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rom_ctrl_smoke 7.320s 221.998us 1 1 100.00
rom_ctrl_stress_all 23.390s 3103.929us 1 1 100.00
rom_ctrl_max_throughput_chk 8.730s 549.937us 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.910s 8502.814us 1 1 100.00
rom_ctrl_kmac_err_chk 15.160s 572.107us 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 198.650s 5262.579us 1 1 100.00
rom_ctrl_sec_cm 241.300s 598.677us 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.240s 4351.488us 1 1 100.00
rom_ctrl_tl_errors 8.930s 629.136us 1 1 100.00
rom_ctrl_tl_intg_err 51.450s 1013.283us 1 1 100.00
rom_ctrl_alert_test 7.660s 288.381us 1 1 100.00
rom_ctrl_mem_walk 6.790s 210.505us 1 1 100.00
rom_ctrl_mem_partial_access 6.010s 650.003us 1 1 100.00
rom_ctrl_csr_hw_reset 8.300s 209.804us 1 1 100.00
rom_ctrl_csr_rw 7.620s 289.528us 1 1 100.00
rom_ctrl_csr_bit_bash 10.360s 1056.861us 1 1 100.00
rom_ctrl_csr_aliasing 6.980s 545.293us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.170s 210.748us 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 9.400s 3213.885us 1 1 100.00