Simulation Results: rstmgr

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.46 %
  • code
  • 99.46 %
  • assert
  • 98.66 %
  • func
  • 97.26 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.10 %
  • toggle
  • 99.41 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rstmgr_smoke 1.420s 257.530us 1 1 100.00
rstmgr_por_stretcher 0.820s 158.443us 1 1 100.00
rstmgr_reset 5.700s 2089.376us 1 1 100.00
rstmgr_sw_rst_reset_race 1.330s 274.445us 1 1 100.00
rstmgr_sw_rst 1.560s 155.577us 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.070s 187.987us 1 1 100.00
rstmgr_leaf_rst_cnsty 4.430s 1273.833us 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.170s 302.657us 1 1 100.00
rstmgr_stress_all 5.870s 2333.500us 1 1 100.00
rstmgr_sec_cm 9.440s 8651.185us 1 1 100.00
rstmgr_tl_errors 2.740s 650.114us 1 1 100.00
rstmgr_tl_intg_err 2.670s 958.820us 1 1 100.00
rstmgr_alert_test 0.890s 72.650us 1 1 100.00
rstmgr_csr_hw_reset 0.870s 145.065us 1 1 100.00
rstmgr_csr_rw 0.900s 70.035us 1 1 100.00
rstmgr_csr_bit_bash 9.120s 2646.305us 1 1 100.00
rstmgr_csr_aliasing 2.800s 439.327us 1 1 100.00
rstmgr_same_csr_outstanding 1.300s 242.075us 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.100s 133.917us 1 1 100.00