Simulation Results: rv_timer

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.27 %
  • code
  • 99.92 %
  • assert
  • 96.82 %
  • func
  • 92.06 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.69 %
  • toggle
  • 100.00 %
Validation stages
unmapped
78.95%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 15 19 78.95
rv_timer_random 0.690s 90.291us 1 1 100.00
rv_timer_min 0.650s 280.192us 0 1 0.00
rv_timer_max 0.880s 44.334us 0 1 0.00
rv_timer_disabled 1.190s 604.219us 1 1 100.00
rv_timer_cfg_update_on_fly 171.050s 501064.586us 1 1 100.00
rv_timer_random_reset 0.650s 110.271us 0 1 0.00
rv_timer_stress_all_with_rand_reset 22.050s 26798.802us 0 1 0.00
rv_timer_stress_all 3.710s 6448.619us 1 1 100.00
rv_timer_sec_cm 0.910s 764.110us 1 1 100.00
rv_timer_tl_errors 1.830s 119.271us 1 1 100.00
rv_timer_tl_intg_err 1.160s 205.083us 1 1 100.00
rv_timer_intr_test 0.620s 11.711us 1 1 100.00
rv_timer_alert_test 0.580s 12.240us 1 1 100.00
rv_timer_csr_hw_reset 0.620s 23.055us 1 1 100.00
rv_timer_csr_rw 0.650s 185.131us 1 1 100.00
rv_timer_csr_bit_bash 2.040s 1137.496us 1 1 100.00
rv_timer_csr_aliasing 0.690s 48.173us 1 1 100.00
rv_timer_same_csr_outstanding 0.750s 26.367us 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.860s 56.493us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 85487577019203868757998666506820248252657318689448346103873358025480411545891 75
UVM_INFO @ 280191871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 71465532792052902525114407983750177264499557912534027085321915596972658268032 75
UVM_INFO @ 110271326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 45077640857456254784922225874816036476651271192268302307240513022756612764965 75
UVM_INFO @ 44333894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
rv_timer_stress_all_with_rand_reset 115196278148216118516572658239453445791609758274334540548339105403800787402719 321
UVM_INFO @ 26798802497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---