Simulation Results

unmapped

31/31 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				31	31	100.00
	sram_ctrl_smoke	5.000s	703.352us	1	1	100.00
	sram_ctrl_multiple_keys	30.000s	27956.861us	1	1	100.00
	sram_ctrl_bijection	115.000s	2994.940us	1	1	100.00
	sram_ctrl_stress_pipeline	177.000s	5320.115us	1	1	100.00
	sram_ctrl_partial_access	3.000s	1425.804us	1	1	100.00
	sram_ctrl_partial_access_b2b	235.000s	19516.571us	1	1	100.00
	sram_ctrl_max_throughput	6.000s	691.664us	1	1	100.00
	sram_ctrl_throughput_w_partial_write	6.000s	5121.081us	1	1	100.00
	sram_ctrl_throughput_w_readback	6.000s	2792.300us	1	1	100.00
	sram_ctrl_lc_escalation	22.000s	6747.609us	1	1	100.00
	sram_ctrl_access_during_key_req	41.000s	9705.402us	1	1	100.00
	sram_ctrl_executable	31.000s	27326.493us	1	1	100.00
	sram_ctrl_regwen	9.000s	485.656us	1	1	100.00
	sram_ctrl_ram_cfg	3.000s	1351.888us	1	1	100.00
	sram_ctrl_mem_walk	81.000s	4208.405us	1	1	100.00
	sram_ctrl_mem_partial_access	94.000s	19875.072us	1	1	100.00
	sram_ctrl_readback_err	5.000s	4159.542us	1	1	100.00
	sram_ctrl_mubi_enc_err	5.000s	699.697us	1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	31.000s	1075.285us	1	1	100.00
	sram_ctrl_stress_all	137.000s	8288.935us	1	1	100.00
	sram_ctrl_sec_cm	4.000s	1040.011us	1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	14.000s	3774.734us	1	1	100.00
	sram_ctrl_tl_errors	3.000s	29.370us	1	1	100.00
	sram_ctrl_tl_intg_err	3.000s	694.684us	1	1	100.00
	sram_ctrl_alert_test	1.000s	13.295us	1	1	100.00
	sram_ctrl_csr_hw_reset	1.000s	39.449us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	13.612us	1	1	100.00
	sram_ctrl_csr_bit_bash	2.000s	254.925us	1	1	100.00
	sram_ctrl_csr_aliasing	1.000s	90.654us	1	1	100.00
	sram_ctrl_same_csr_outstanding	1.000s	211.445us	1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.000s	1310.594us	1	1	100.00

Simulation Results: sram_ctrl/main