Simulation Results

unmapped

31/31 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				31	31	100.00
	sram_ctrl_smoke	2.000s	136.330us	1	1	100.00
	sram_ctrl_multiple_keys	10.000s	1047.451us	1	1	100.00
	sram_ctrl_bijection	7.000s	8590.415us	1	1	100.00
	sram_ctrl_stress_pipeline	122.000s	2494.050us	1	1	100.00
	sram_ctrl_partial_access	2.000s	829.022us	1	1	100.00
	sram_ctrl_partial_access_b2b	110.000s	5926.148us	1	1	100.00
	sram_ctrl_max_throughput	2.000s	84.436us	1	1	100.00
	sram_ctrl_throughput_w_partial_write	2.000s	137.610us	1	1	100.00
	sram_ctrl_throughput_w_readback	1.000s	150.526us	1	1	100.00
	sram_ctrl_lc_escalation	6.000s	551.245us	1	1	100.00
	sram_ctrl_access_during_key_req	13.000s	1998.639us	1	1	100.00
	sram_ctrl_executable	4.000s	187.342us	1	1	100.00
	sram_ctrl_regwen	9.000s	371.313us	1	1	100.00
	sram_ctrl_ram_cfg	1.000s	32.384us	1	1	100.00
	sram_ctrl_mem_walk	9.000s	681.263us	1	1	100.00
	sram_ctrl_mem_partial_access	3.000s	101.935us	1	1	100.00
	sram_ctrl_readback_err	2.000s	213.370us	1	1	100.00
	sram_ctrl_mubi_enc_err	1.000s	102.641us	1	1	100.00
	sram_ctrl_stress_all_with_rand_reset	18.000s	2068.624us	1	1	100.00
	sram_ctrl_stress_all	17.000s	2207.964us	1	1	100.00
	sram_ctrl_sec_cm	3.000s	1767.433us	1	1	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.000s	635.085us	1	1	100.00
	sram_ctrl_tl_errors	3.000s	623.113us	1	1	100.00
	sram_ctrl_tl_intg_err	3.000s	783.280us	1	1	100.00
	sram_ctrl_alert_test	1.000s	33.772us	1	1	100.00
	sram_ctrl_csr_hw_reset	1.000s	23.859us	1	1	100.00
	sram_ctrl_csr_rw	1.000s	13.264us	1	1	100.00
	sram_ctrl_csr_bit_bash	2.000s	173.258us	1	1	100.00
	sram_ctrl_csr_aliasing	2.000s	165.359us	1	1	100.00
	sram_ctrl_same_csr_outstanding	2.000s	35.754us	1	1	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	1.000s	42.993us	1	1	100.00

Simulation Results: sram_ctrl/ret