Simulation Results: sysrst_ctrl

 
26/05/2026 15:30:30 DVSim: v1.49.6 sha: cbf0611 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.80 %
  • code
  • 92.06 %
  • assert
  • 91.86 %
  • func
  • 64.49 %
  • line
  • 96.89 %
  • branch
  • 97.11 %
  • cond
  • 93.67 %
  • toggle
  • 99.54 %
  • FSM
  • 73.08 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 27 27 100.00
sysrst_ctrl_smoke 4.130s 2111.736us 1 1 100.00
sysrst_ctrl_in_out_inverted 5.720s 2484.828us 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.420s 2408.786us 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.030s 2529.001us 1 1 100.00
sysrst_ctrl_pin_access_test 2.650s 2089.327us 1 1 100.00
sysrst_ctrl_pin_override_test 1.820s 2524.786us 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.350s 2612.620us 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 7.500s 3960.763us 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.380s 3380.289us 1 1 100.00
sysrst_ctrl_ultra_low_pwr 3.850s 7130.195us 1 1 100.00
sysrst_ctrl_combo_detect 173.440s 87792.413us 1 1 100.00
sysrst_ctrl_edge_detect 2.240s 4175.143us 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 10.530s 26396.973us 1 1 100.00
sysrst_ctrl_feature_disable 57.470s 32613.399us 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.290s 3155.769us 1 1 100.00
sysrst_ctrl_stress_all 16.300s 9437.995us 1 1 100.00
sysrst_ctrl_sec_cm 26.730s 42289.261us 1 1 100.00
sysrst_ctrl_tl_errors 7.460s 2062.960us 1 1 100.00
sysrst_ctrl_tl_intg_err 8.250s 22599.177us 1 1 100.00
sysrst_ctrl_alert_test 2.170s 2042.526us 1 1 100.00
sysrst_ctrl_intr_test 1.690s 2036.850us 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.220s 4041.626us 1 1 100.00
sysrst_ctrl_csr_rw 2.190s 2066.965us 1 1 100.00
sysrst_ctrl_csr_bit_bash 39.560s 38934.802us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.480s 3252.895us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.830s 4586.254us 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.960s 2077.235us 1 1 100.00