Simulation Results

Simulation Results: adc_ctrl

27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
66.23 %

code
93.26 %

assert
92.06 %

func
13.36 %

line
98.00 %

branch
96.29 %

cond
85.98 %

toggle
99.53 %

FSM
86.49 %

Validation stages

unmapped

64.00%

unmapped

16/25 passed

64.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				16	25	64.00
	adc_ctrl_smoke	5.020s	5838.213us	1	1	100.00
	adc_ctrl_filters_polled	0.810s	286.544us	0	1	0.00
	adc_ctrl_filters_polled_fixed	1.010s	336.215us	0	1	0.00
	adc_ctrl_filters_interrupt	1.020s	303.081us	0	1	0.00
	adc_ctrl_filters_interrupt_fixed	0.870s	298.083us	0	1	0.00
	adc_ctrl_filters_wakeup	1.320s	437.274us	0	1	0.00
	adc_ctrl_filters_wakeup_fixed	0.820s	460.757us	0	1	0.00
	adc_ctrl_clock_gating	1.820s	405.749us	0	1	0.00
	adc_ctrl_filters_both	1.000s	274.273us	0	1	0.00
	adc_ctrl_poweron_counter	4.430s	2840.606us	1	1	100.00
	adc_ctrl_lowpower_counter	34.880s	27016.732us	1	1	100.00
	adc_ctrl_fsm_reset	59.620s	122444.363us	1	1	100.00
	adc_ctrl_stress_all_with_rand_reset	1.300s	699.713us	0	1	0.00
	adc_ctrl_stress_all	19.930s	146084.212us	1	1	100.00
	adc_ctrl_sec_cm	4.670s	4609.649us	1	1	100.00
	adc_ctrl_tl_errors	1.880s	524.874us	1	1	100.00
	adc_ctrl_tl_intg_err	16.710s	8449.159us	1	1	100.00
	adc_ctrl_intr_test	1.310s	320.019us	1	1	100.00
	adc_ctrl_alert_test	1.290s	416.380us	1	1	100.00
	adc_ctrl_csr_hw_reset	1.310s	1191.905us	1	1	100.00
	adc_ctrl_csr_rw	1.130s	371.730us	1	1	100.00
	adc_ctrl_csr_bit_bash	28.320s	53051.296us	1	1	100.00
	adc_ctrl_csr_aliasing	3.880s	1126.526us	1	1	100.00
	adc_ctrl_same_csr_outstanding	4.010s	4179.657us	1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.620s	475.475us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				9 test runs
	adc_ctrl_filters_polled	1357282393809797147792680802610273433676502729031943252291432900208231506999	388	UVM_INFO @ 286543871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	51915705428438171787997365482611063857328749747108095324586531812417789300449	388	UVM_INFO @ 336215320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	8304500149583169005419908744585932814328167287836846292499110634364415362854	388	UVM_INFO @ 303080860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	11529470208891265934956804489007635506513890377326972707476164684362814626840	388	UVM_INFO @ 298083033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	37976892000534779807567197076648281566649694618243597945254847030282437350436	388	UVM_INFO @ 437273961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	44363706271919623153762093939244443714503490936428981184689613556613173303564	388	UVM_INFO @ 460756509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	92176785543139116697234070379772678350959244482332320789424833911453927970908	388	UVM_INFO @ 405749323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	90274921625362076265496116613449595268402759875912405667016389664470290118385	388	UVM_INFO @ 274272909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	65880289727248896391227828717353565537468318107736528641120882534139650051136	394	UVM_INFO @ 699712813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---