| unmapped |
|
96.88% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 31 | 32 | 96.88 | |||
| aes_wake_up | 2.000s | 73.648us | 1 | 1 | 100.00 | |
| aes_nist_vectors | 4.000s | 784.367us | 1 | 1 | 100.00 | |
| aes_deinit | 2.000s | 133.667us | 1 | 1 | 100.00 | |
| aes_man_cfg_err | 1.000s | 79.381us | 1 | 1 | 100.00 | |
| aes_readability | 1.000s | 53.306us | 1 | 1 | 100.00 | |
| aes_smoke | 2.000s | 59.941us | 1 | 1 | 100.00 | |
| aes_config_error | 2.000s | 84.231us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 103.757us | 1 | 1 | 100.00 | |
| aes_b2b | 2.000s | 74.941us | 1 | 1 | 100.00 | |
| aes_clear | 2.000s | 56.375us | 1 | 1 | 100.00 | |
| aes_alert_reset | 3.000s | 419.242us | 1 | 1 | 100.00 | |
| aes_sideload | 2.000s | 499.910us | 1 | 1 | 100.00 | |
| aes_reseed | 2.000s | 178.911us | 1 | 1 | 100.00 | |
| aes_fi | 2.000s | 73.563us | 1 | 1 | 100.00 | |
| aes_control_fi | 1.000s | 53.018us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 47.899us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 57.481us | 1 | 1 | 100.00 | |
| aes_core_fi | 2.000s | 75.233us | 1 | 1 | 100.00 | |
| aes_stress_all | 8.000s | 266.991us | 1 | 1 | 100.00 | |
| aes_stress_all_with_rand_reset | 7.000s | 51.739us | 0 | 1 | 0.00 | |
| aes_sec_cm | 2.000s | 786.196us | 1 | 1 | 100.00 | |
| aes_tl_errors | 2.000s | 100.464us | 1 | 1 | 100.00 | |
| aes_tl_intg_err | 3.000s | 547.187us | 1 | 1 | 100.00 | |
| aes_shadow_reg_errors | 2.000s | 82.876us | 1 | 1 | 100.00 | |
| aes_shadow_reg_errors_with_csr_rw | 3.000s | 258.374us | 1 | 1 | 100.00 | |
| aes_csr_hw_reset | 2.000s | 61.333us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 71.263us | 1 | 1 | 100.00 | |
| aes_csr_bit_bash | 3.000s | 1063.728us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 2.000s | 153.877us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 94.458us | 1 | 1 | 100.00 | |
| aes_csr_mem_rw_with_rand_reset | 2.000s | 76.895us | 1 | 1 | 100.00 | |
| aes_alert_test | 1.000s | 60.459us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1142): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) | 1 test run | |||
| aes_stress_all_with_rand_reset | 112761024364117103788020527970068203708093288538299357176441019578940554646967 | 154 |
UVM_ERROR @ 51739147 ps: (aes_core.sv:1142) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 51739147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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