| unmapped |
|
88.46% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 23 | 26 | 88.46 | |||
| alert_handler_smoke | 21.560s | 349.809us | 1 | 1 | 100.00 | |
| alert_handler_random_alerts | 12.740s | 1479.531us | 1 | 1 | 100.00 | |
| alert_handler_random_classes | 19.430s | 1154.939us | 1 | 1 | 100.00 | |
| alert_handler_esc_intr_timeout | 31.240s | 2136.708us | 1 | 1 | 100.00 | |
| alert_handler_esc_alert_accum | 9.200s | 659.540us | 1 | 1 | 100.00 | |
| alert_handler_sig_int_fail | 19.040s | 277.034us | 1 | 1 | 100.00 | |
| alert_handler_entropy | 827.690s | 10706.718us | 1 | 1 | 100.00 | |
| alert_handler_ping_timeout | 82.870s | 3571.818us | 0 | 1 | 0.00 | |
| alert_handler_lpg | 1262.000s | 137635.593us | 1 | 1 | 100.00 | |
| alert_handler_lpg_stub_clk | 426.770s | 8531.573us | 1 | 1 | 100.00 | |
| alert_handler_entropy_stress | 17.470s | 643.560us | 0 | 1 | 0.00 | |
| alert_handler_stress_all | 2144.900s | 238179.143us | 1 | 1 | 100.00 | |
| alert_handler_shadow_reg_errors_with_csr_rw | 672.500s | 21872.304us | 1 | 1 | 100.00 | |
| alert_handler_alert_accum_saturation | 1.690s | 38.136us | 1 | 1 | 100.00 | |
| alert_handler_stress_all_with_rand_reset | 63.530s | 1649.674us | 0 | 1 | 0.00 | |
| alert_handler_sec_cm | 8.380s | 181.523us | 1 | 1 | 100.00 | |
| alert_handler_shadow_reg_errors | 88.470s | 2126.603us | 1 | 1 | 100.00 | |
| alert_handler_tl_errors | 4.710s | 312.069us | 1 | 1 | 100.00 | |
| alert_handler_tl_intg_err | 10.380s | 337.474us | 1 | 1 | 100.00 | |
| alert_handler_intr_test | 1.220s | 50.193us | 1 | 1 | 100.00 | |
| alert_handler_csr_hw_reset | 6.120s | 112.284us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 5.960s | 461.633us | 1 | 1 | 100.00 | |
| alert_handler_csr_bit_bash | 169.300s | 4921.766us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 166.670s | 15821.029us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 16.910s | 716.712us | 1 | 1 | 100.00 | |
| alert_handler_csr_mem_rw_with_rand_reset | 4.350s | 271.449us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 1 test run | |||
| alert_handler_ping_timeout | 54004426670827799031146177043580786845691831170472313266115381950587414721462 | 102 |
UVM_INFO @ 3571818347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 1 test run | |||
| alert_handler_entropy_stress | 8046145971373640849643762030928990452337702452702296543331623236732416244206 | 188 |
UVM_INFO @ 643559715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| alert_handler_stress_all_with_rand_reset | 95203289646734938236076067896822762761795064442857486854733923947234976657959 | 127 |
UVM_INFO @ 1649673623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|