Simulation Results: csrng

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.26 %
  • code
  • 92.19 %
  • assert
  • 94.32 %
  • func
  • 75.26 %
  • block
  • 96.92 %
  • line
  • 97.73 %
  • branch
  • 92.35 %
  • toggle
  • 92.97 %
  • FSM
  • 85.71 %
Validation stages
unmapped
89.47%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 17 19 89.47
csrng_smoke 3.000s 74.883us 1 1 100.00
csrng_cmds 2.000s 19.732us 0 1 0.00
csrng_stress_all 219.000s 14645.229us 1 1 100.00
csrng_intr 4.000s 59.242us 1 1 100.00
csrng_alert 10.000s 158.582us 1 1 100.00
csrng_err 2.000s 27.756us 1 1 100.00
csrng_regwen 2.000s 22.094us 1 1 100.00
csrng_stress_all_with_rand_reset 10802.085s 0.000us 0 1 0.00
csrng_sec_cm 3.000s 151.978us 1 1 100.00
csrng_tl_errors 7.000s 331.636us 1 1 100.00
csrng_tl_intg_err 3.000s 71.148us 1 1 100.00
csrng_alert_test 1.000s 21.041us 1 1 100.00
csrng_intr_test 2.000s 42.767us 1 1 100.00
csrng_csr_hw_reset 3.000s 199.673us 1 1 100.00
csrng_csr_rw 3.000s 70.366us 1 1 100.00
csrng_csr_bit_bash 4.000s 134.666us 1 1 100.00
csrng_csr_aliasing 2.000s 44.062us 1 1 100.00
csrng_same_csr_outstanding 3.000s 70.689us 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 26.438us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 69840266239449867477110378108648243251464758041305055030522072257669272393015 100
UVM_INFO @ 19732357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 33922923004386574621094970754065337314773672707100329391165687539483668216541 None