Simulation Results: edn/edn0

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.18 %
  • code
  • 86.17 %
  • assert
  • 97.61 %
  • func
  • 80.75 %
  • line
  • 98.75 %
  • branch
  • 95.96 %
  • cond
  • 89.26 %
  • toggle
  • 90.97 %
  • FSM
  • 55.91 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 21 21 100.00
edn_smoke 0.890s 17.447us 1 1 100.00
edn_regwen 0.900s 20.587us 1 1 100.00
edn_genbits 1.130s 65.229us 1 1 100.00
edn_stress_all 1.760s 218.655us 1 1 100.00
edn_stress_all_with_rand_reset 33.480s 8135.198us 1 1 100.00
edn_intr 0.820s 36.763us 1 1 100.00
edn_alert 1.090s 98.801us 1 1 100.00
edn_err 0.930s 46.388us 1 1 100.00
edn_disable 0.840s 38.932us 1 1 100.00
edn_disable_auto_req_mode 1.120s 46.226us 1 1 100.00
edn_sec_cm 3.400s 537.078us 1 1 100.00
edn_tl_errors 1.580s 98.722us 1 1 100.00
edn_tl_intg_err 1.890s 649.603us 1 1 100.00
edn_alert_test 0.940s 20.030us 1 1 100.00
edn_intr_test 0.750s 155.866us 1 1 100.00
edn_csr_hw_reset 0.870s 21.792us 1 1 100.00
edn_csr_rw 0.810s 22.640us 1 1 100.00
edn_csr_bit_bash 1.650s 36.415us 1 1 100.00
edn_csr_aliasing 0.990s 14.439us 1 1 100.00
edn_same_csr_outstanding 1.140s 42.337us 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.080s 58.169us 1 1 100.00