Simulation Results: hmac

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.32 %
  • code
  • 97.80 %
  • assert
  • 97.80 %
  • func
  • 45.36 %
  • line
  • 99.64 %
  • branch
  • 99.34 %
  • cond
  • 95.90 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 28 28 100.00
hmac_smoke 11.550s 1203.879us 1 1 100.00
hmac_long_msg 20.470s 879.303us 1 1 100.00
hmac_stress_reset 2.610s 71.043us 1 1 100.00
hmac_back_pressure 33.980s 849.966us 1 1 100.00
hmac_datapath_stress 815.570s 11557.847us 1 1 100.00
hmac_burst_wr 8.350s 843.987us 1 1 100.00
hmac_error 68.610s 10248.722us 1 1 100.00
hmac_wipe_secret 60.790s 6037.431us 1 1 100.00
hmac_test_sha256_vectors 174.650s 26180.034us 1 1 100.00
hmac_test_sha384_vectors 452.920s 65559.593us 1 1 100.00
hmac_test_sha512_vectors 20.340s 260.502us 1 1 100.00
hmac_test_hmac256_vectors 6.280s 936.822us 1 1 100.00
hmac_test_hmac384_vectors 12.080s 409.901us 1 1 100.00
hmac_test_hmac512_vectors 8.440s 535.845us 1 1 100.00
hmac_stress_all 341.990s 69725.018us 1 1 100.00
hmac_stress_all_with_rand_reset 190.180s 4617.508us 1 1 100.00
hmac_directed 0.740s 52.310us 1 1 100.00
hmac_sec_cm 0.980s 571.414us 1 1 100.00
hmac_tl_errors 1.890s 340.644us 1 1 100.00
hmac_tl_intg_err 2.220s 131.559us 1 1 100.00
hmac_intr_test 0.690s 17.901us 1 1 100.00
hmac_alert_test 0.580s 43.789us 1 1 100.00
hmac_csr_hw_reset 0.930s 31.974us 1 1 100.00
hmac_csr_rw 0.750s 55.061us 1 1 100.00
hmac_csr_bit_bash 8.800s 4309.086us 1 1 100.00
hmac_csr_aliasing 3.760s 1673.932us 1 1 100.00
hmac_same_csr_outstanding 1.280s 32.987us 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.220s 36.862us 1 1 100.00