| unmapped |
|
96.67% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 29 | 30 | 96.67 | |||
| keymgr_smoke | 3.340s | 216.089us | 1 | 1 | 100.00 | |
| keymgr_sideload | 2.770s | 151.469us | 1 | 1 | 100.00 | |
| keymgr_sideload_kmac | 4.080s | 787.329us | 1 | 1 | 100.00 | |
| keymgr_sideload_aes | 5.440s | 409.434us | 1 | 1 | 100.00 | |
| keymgr_sideload_otbn | 2.570s | 75.483us | 1 | 1 | 100.00 | |
| keymgr_random | 3.420s | 199.769us | 1 | 1 | 100.00 | |
| keymgr_cfg_regwen | 2.590s | 170.990us | 1 | 1 | 100.00 | |
| keymgr_direct_to_disabled | 2.390s | 30.157us | 1 | 1 | 100.00 | |
| keymgr_lc_disable | 2.420s | 177.937us | 1 | 1 | 100.00 | |
| keymgr_sw_invalid_input | 4.420s | 143.665us | 1 | 1 | 100.00 | |
| keymgr_hwsw_invalid_input | 1.750s | 107.961us | 1 | 1 | 100.00 | |
| keymgr_kmac_rsp_err | 2.390s | 424.372us | 1 | 1 | 100.00 | |
| keymgr_custom_cm | 2.100s | 989.078us | 1 | 1 | 100.00 | |
| keymgr_sideload_protect | 1.700s | 31.401us | 1 | 1 | 100.00 | |
| keymgr_sync_async_fault_cross | 1.920s | 260.534us | 1 | 1 | 100.00 | |
| keymgr_stress_all | 19.320s | 885.278us | 1 | 1 | 100.00 | |
| keymgr_stress_all_with_rand_reset | 3.580s | 214.520us | 0 | 1 | 0.00 | |
| keymgr_sec_cm | 9.270s | 2487.520us | 1 | 1 | 100.00 | |
| keymgr_shadow_reg_errors | 3.160s | 500.589us | 1 | 1 | 100.00 | |
| keymgr_shadow_reg_errors_with_csr_rw | 4.090s | 409.225us | 1 | 1 | 100.00 | |
| keymgr_tl_errors | 2.420s | 337.872us | 1 | 1 | 100.00 | |
| keymgr_tl_intg_err | 3.470s | 125.052us | 1 | 1 | 100.00 | |
| keymgr_alert_test | 0.720s | 15.479us | 1 | 1 | 100.00 | |
| keymgr_intr_test | 0.720s | 14.998us | 1 | 1 | 100.00 | |
| keymgr_csr_hw_reset | 1.160s | 95.204us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 1.090s | 41.707us | 1 | 1 | 100.00 | |
| keymgr_csr_bit_bash | 8.070s | 767.896us | 1 | 1 | 100.00 | |
| keymgr_csr_aliasing | 5.450s | 128.661us | 1 | 1 | 100.00 | |
| keymgr_same_csr_outstanding | 1.470s | 54.639us | 1 | 1 | 100.00 | |
| keymgr_csr_mem_rw_with_rand_reset | 1.760s | 92.067us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| keymgr_stress_all_with_rand_reset | 24332801174467330802672742051074135056544967106852488194260294364242655033750 | 461 |
UVM_INFO @ 214520444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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