Simulation Results: lc_ctrl/volatile_unlock_disabled

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.93 %
  • code
  • 84.24 %
  • assert
  • 94.97 %
  • func
  • 93.59 %
  • line
  • 97.19 %
  • branch
  • 93.85 %
  • cond
  • 79.38 %
  • toggle
  • 86.27 %
  • FSM
  • 64.49 %
Validation stages
unmapped
97.44%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 38 39 97.44
lc_ctrl_smoke 2.360s 127.788us 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.150s 43.185us 1 1 100.00
lc_ctrl_state_failure 8.080s 623.053us 1 1 100.00
lc_ctrl_state_post_trans 3.700s 139.553us 1 1 100.00
lc_ctrl_prog_failure 2.640s 150.978us 1 1 100.00
lc_ctrl_errors 8.540s 543.650us 1 1 100.00
lc_ctrl_security_escalation 6.580s 488.354us 1 1 100.00
lc_ctrl_regwen_during_op 8.710s 440.296us 1 1 100.00
lc_ctrl_claim_transition_if 0.780s 100.624us 1 1 100.00
lc_ctrl_jtag_smoke 2.500s 403.837us 1 1 100.00
lc_ctrl_jtag_state_failure 16.230s 1018.235us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.260s 410.668us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.550s 402.215us 1 1 100.00
lc_ctrl_jtag_errors 16.040s 1566.054us 1 1 100.00
lc_ctrl_jtag_access 5.570s 1347.258us 1 1 100.00
lc_ctrl_jtag_priority 2.850s 463.976us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.330s 584.847us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.220s 167.345us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.070s 182.173us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.390s 673.443us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 11.510s 638.708us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.580s 87.475us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.550s 2613.916us 1 1 100.00
lc_ctrl_jtag_alert_test 1.850s 49.224us 1 1 100.00
lc_ctrl_sec_mubi 4.030s 3060.520us 1 1 100.00
lc_ctrl_sec_token_mux 5.710s 281.009us 1 1 100.00
lc_ctrl_sec_token_digest 7.990s 633.017us 1 1 100.00
lc_ctrl_stress_all 48.180s 2216.176us 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 28.330s 15082.527us 0 1 0.00
lc_ctrl_sec_cm 7.980s 235.396us 1 1 100.00
lc_ctrl_tl_errors 3.160s 1329.421us 1 1 100.00
lc_ctrl_tl_intg_err 1.210s 403.011us 1 1 100.00
lc_ctrl_alert_test 1.090s 58.110us 1 1 100.00
lc_ctrl_csr_hw_reset 0.840s 17.255us 1 1 100.00
lc_ctrl_csr_rw 1.310s 51.206us 1 1 100.00
lc_ctrl_csr_bit_bash 2.530s 429.551us 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 63.984us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.250s 71.988us 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.010s 28.412us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 11498837543426761734454696513995272499400797495312183606808880834991507166234 8131
UVM_INFO @ 15082526791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---