Simulation Results: lc_ctrl/volatile_unlock_enabled

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.84 %
  • code
  • 83.50 %
  • assert
  • 94.55 %
  • func
  • 91.46 %
  • line
  • 97.17 %
  • branch
  • 93.80 %
  • cond
  • 79.01 %
  • toggle
  • 86.79 %
  • FSM
  • 60.75 %
Validation stages
unmapped
97.44%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 38 39 97.44
lc_ctrl_smoke 1.520s 149.451us 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.940s 41.244us 1 1 100.00
lc_ctrl_state_failure 6.850s 635.717us 1 1 100.00
lc_ctrl_state_post_trans 2.940s 343.812us 1 1 100.00
lc_ctrl_prog_failure 2.130s 252.562us 1 1 100.00
lc_ctrl_errors 5.470s 394.636us 1 1 100.00
lc_ctrl_security_escalation 4.470s 338.032us 1 1 100.00
lc_ctrl_regwen_during_op 13.570s 5567.312us 1 1 100.00
lc_ctrl_claim_transition_if 1.010s 14.422us 1 1 100.00
lc_ctrl_jtag_smoke 4.690s 665.651us 1 1 100.00
lc_ctrl_jtag_state_failure 30.700s 5794.736us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.450s 2041.220us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.820s 177.202us 1 1 100.00
lc_ctrl_jtag_errors 31.540s 3582.101us 1 1 100.00
lc_ctrl_jtag_access 3.860s 526.158us 1 1 100.00
lc_ctrl_jtag_priority 3.730s 742.421us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.950s 3741.727us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.150s 228.218us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.090s 334.178us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.760s 1599.216us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 12.960s 8229.291us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.900s 102.510us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.870s 115.225us 1 1 100.00
lc_ctrl_jtag_alert_test 1.180s 25.337us 1 1 100.00
lc_ctrl_sec_mubi 11.340s 529.761us 1 1 100.00
lc_ctrl_sec_token_mux 7.840s 320.744us 1 1 100.00
lc_ctrl_sec_token_digest 8.140s 1783.921us 1 1 100.00
lc_ctrl_stress_all 38.910s 3674.766us 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 6.540s 3708.906us 0 1 0.00
lc_ctrl_sec_cm 10.600s 401.754us 1 1 100.00
lc_ctrl_tl_errors 1.920s 30.403us 1 1 100.00
lc_ctrl_tl_intg_err 1.540s 241.403us 1 1 100.00
lc_ctrl_alert_test 1.010s 20.874us 1 1 100.00
lc_ctrl_csr_hw_reset 0.800s 37.104us 1 1 100.00
lc_ctrl_csr_rw 0.910s 46.259us 1 1 100.00
lc_ctrl_csr_bit_bash 1.460s 243.204us 1 1 100.00
lc_ctrl_csr_aliasing 1.020s 20.780us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.550s 46.706us 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.300s 198.717us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 94879177700370653587031354332266645225293746678716397417858310741564362452707 905
UVM_INFO @ 3708905579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---