Simulation Results: otbn

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.19 %
  • code
  • 94.27 %
  • assert
  • 90.43 %
  • func
  • 97.88 %
  • block
  • 99.33 %
  • line
  • 99.49 %
  • branch
  • 91.66 %
  • toggle
  • 88.37 %
  • FSM
  • 97.56 %
Validation stages
unmapped
92.86%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 39 42 92.86
otbn_smoke 10.000s 44.050us 1 1 100.00
otbn_smoke_vectorized 8.000s 52.485us 1 1 100.00
otbn_single 7.000s 47.122us 1 1 100.00
otbn_multi 35.000s 216.072us 1 1 100.00
otbn_reset 21.000s 135.273us 1 1 100.00
otbn_multi_err 47.000s 377.801us 1 1 100.00
otbn_imem_err 17.000s 21.421us 1 1 100.00
otbn_dmem_err 21.000s 53.607us 1 1 100.00
otbn_escalate 28.000s 51.531us 1 1 100.00
otbn_alu_bignum_mod_err 37.000s 257.535us 1 1 100.00
otbn_controller_ispr_rdata_err 36.000s 40.319us 0 1 0.00
otbn_mac_bignum_acc_err 6.000s 16.251us 1 1 100.00
otbn_rf_bignum_intg_err 6.000s 418.720us 1 1 100.00
otbn_rf_base_intg_err 10.000s 85.713us 1 1 100.00
otbn_stress_all 48.000s 557.261us 1 1 100.00
otbn_stress_all_with_rand_reset 117.000s 2506.836us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 38.813us 1 1 100.00
otbn_illegal_mem_acc 16.000s 10.510us 1 1 100.00
otbn_sw_errs_fatal_chk 13.000s 41.693us 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 17.827us 1 1 100.00
otbn_rnd_sec_cm 42.000s 837.385us 1 1 100.00
otbn_ctrl_redun 23.000s 30.750us 1 1 100.00
otbn_sec_wipe_err 9.000s 69.695us 1 1 100.00
otbn_urnd_err 4.000s 10.217us 0 1 0.00
otbn_sw_no_acc 15.000s 197.175us 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 19.323us 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 4.665us 0 1 0.00
otbn_partial_wipe 5.000s 72.263us 1 1 100.00
otbn_passthru_mem_tl_intg_err 26.000s 119.941us 1 1 100.00
otbn_sec_cm 119.000s 1351.916us 1 1 100.00
otbn_tl_errors 5.000s 91.715us 1 1 100.00
otbn_tl_intg_err 19.000s 229.853us 1 1 100.00
otbn_intr_test 9.000s 42.712us 1 1 100.00
otbn_alert_test 31.000s 23.133us 1 1 100.00
otbn_mem_walk 61.000s 13619.705us 1 1 100.00
otbn_mem_partial_access 14.000s 176.104us 1 1 100.00
otbn_csr_hw_reset 30.000s 47.890us 1 1 100.00
otbn_csr_rw 30.000s 16.319us 1 1 100.00
otbn_csr_bit_bash 31.000s 48.901us 1 1 100.00
otbn_csr_aliasing 30.000s 47.815us 1 1 100.00
otbn_same_csr_outstanding 4.000s 35.588us 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 32.000s 67.179us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_controller_ispr_rdata_err 40832853875615209968255884121240836714977808999240485013171831498040619372367 111
UVM_INFO @ 40319222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_urnd_err 81400721299073739120537494866193022644589029077509440085579415342952302684493 109
UVM_INFO @ 10217025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 15007860633901322623263957716246732113607389229382878260008740211573819473864 117
UVM_ERROR @ 4665170 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 4665170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---