| unmapped |
|
93.33% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 28 | 30 | 93.33 | |||
| otp_ctrl_wake_up | 1.620s | 98.274us | 1 | 1 | 100.00 | |
| otp_ctrl_smoke | 3.770s | 185.831us | 1 | 1 | 100.00 | |
| otp_ctrl_partition_walk | 14.170s | 1770.061us | 1 | 1 | 100.00 | |
| otp_ctrl_low_freq_read | 10.410s | 8253.362us | 1 | 1 | 100.00 | |
| otp_ctrl_init_fail | 3.400s | 758.151us | 1 | 1 | 100.00 | |
| otp_ctrl_background_chks | 7.820s | 952.207us | 1 | 1 | 100.00 | |
| otp_ctrl_parallel_lc_req | 9.120s | 8802.709us | 1 | 1 | 100.00 | |
| otp_ctrl_parallel_lc_esc | 2.140s | 279.320us | 1 | 1 | 100.00 | |
| otp_ctrl_dai_lock | 15.640s | 14136.256us | 1 | 1 | 100.00 | |
| otp_ctrl_dai_errs | 10.900s | 635.103us | 1 | 1 | 100.00 | |
| otp_ctrl_check_fail | 3.010s | 133.111us | 1 | 1 | 100.00 | |
| otp_ctrl_macro_errs | 9.880s | 1371.572us | 0 | 1 | 0.00 | |
| otp_ctrl_parallel_key_req | 27.380s | 3370.343us | 1 | 1 | 100.00 | |
| otp_ctrl_regwen | 3.570s | 1648.327us | 1 | 1 | 100.00 | |
| otp_ctrl_test_access | 8.290s | 1746.600us | 1 | 1 | 100.00 | |
| otp_ctrl_stress_all_with_rand_reset | 1.080s | 25.996us | 0 | 1 | 0.00 | |
| otp_ctrl_stress_all | 18.550s | 1473.697us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 110.170s | 11922.707us | 1 | 1 | 100.00 | |
| otp_ctrl_tl_errors | 5.630s | 2236.385us | 1 | 1 | 100.00 | |
| otp_ctrl_tl_intg_err | 11.830s | 10540.516us | 1 | 1 | 100.00 | |
| otp_ctrl_alert_test | 2.040s | 203.662us | 1 | 1 | 100.00 | |
| otp_ctrl_intr_test | 1.320s | 79.224us | 1 | 1 | 100.00 | |
| otp_ctrl_mem_walk | 1.740s | 43.329us | 1 | 1 | 100.00 | |
| otp_ctrl_mem_partial_access | 1.600s | 84.229us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_hw_reset | 2.060s | 402.432us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_rw | 1.760s | 698.860us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_bit_bash | 8.310s | 2168.631us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 2.830s | 167.787us | 1 | 1 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 2.330s | 93.087us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_mem_rw_with_rand_reset | 1.920s | 142.886us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* | 1 test run | |||
| otp_ctrl_macro_errs | 60588625077666413024162616506088281302551036714825985452536699398444845130332 | 6555 |
UVM_INFO @ 1371571666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | 1 test run | |||
| otp_ctrl_stress_all_with_rand_reset | 30256644508472825663571720697187913209105205482608131283062114652644297228787 | 93 |
UVM_INFO @ 25995851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|