Simulation Results: rom_ctrl/32kb

 
27/05/2026 15:30:30 DVSim: v1.49.6 sha: d967e2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.24 %
  • code
  • 97.91 %
  • assert
  • 97.38 %
  • func
  • 96.42 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 98.07 %
  • toggle
  • 99.80 %
  • FSM
  • 93.33 %
Validation stages
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 19 100.00
rom_ctrl_smoke 3.800s 1641.484us 1 1 100.00
rom_ctrl_stress_all 12.170s 449.288us 1 1 100.00
rom_ctrl_max_throughput_chk 5.190s 176.490us 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 50.890s 1398.069us 1 1 100.00
rom_ctrl_kmac_err_chk 6.410s 302.816us 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 46.340s 1537.089us 1 1 100.00
rom_ctrl_sec_cm 123.850s 1788.387us 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.690s 2292.417us 1 1 100.00
rom_ctrl_tl_errors 6.040s 229.339us 1 1 100.00
rom_ctrl_tl_intg_err 23.640s 3633.880us 1 1 100.00
rom_ctrl_alert_test 3.770s 132.797us 1 1 100.00
rom_ctrl_mem_walk 4.060s 171.479us 1 1 100.00
rom_ctrl_mem_partial_access 3.360s 134.718us 1 1 100.00
rom_ctrl_csr_hw_reset 5.160s 381.403us 1 1 100.00
rom_ctrl_csr_rw 3.460s 791.102us 1 1 100.00
rom_ctrl_csr_bit_bash 3.780s 575.453us 1 1 100.00
rom_ctrl_csr_aliasing 3.600s 558.983us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.190s 358.135us 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.150s 129.790us 1 1 100.00